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209f68be3c
Rule 8.6 requires each identifier with external linkage to have exactly one external definitions. Rule 10.x necessitates operands to have essential type; left and right operands should be of same width and type. Rule 17.7 requires function return value to be checked for error information. This patch fixes above mentioned errors in nvgpu.hal.mc. Jira NVGPU-3855 Change-Id: I5440392de5d55dc98ed2002273af8a44a596cd3a Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2162145 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
53 lines
2.0 KiB
C
53 lines
2.0 KiB
C
/*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef MC_GP10B_H
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#define MC_GP10B_H
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#include <nvgpu/types.h>
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#define MAX_MC_INTR_REGS 2U
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struct gk20a;
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enum nvgpu_unit;
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void mc_gp10b_intr_mask(struct gk20a *g);
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void mc_gp10b_intr_pmu_unit_config(struct gk20a *g, bool enable);
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void mc_gp10b_isr_stall(struct gk20a *g);
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bool mc_gp10b_is_intr1_pending(struct gk20a *g,
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enum nvgpu_unit unit, u32 mc_intr_1);
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void mc_gp10b_log_pending_intrs(struct gk20a *g);
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u32 mc_gp10b_intr_stall(struct gk20a *g);
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void mc_gp10b_intr_stall_pause(struct gk20a *g);
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void mc_gp10b_intr_stall_resume(struct gk20a *g);
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u32 mc_gp10b_intr_nonstall(struct gk20a *g);
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void mc_gp10b_intr_nonstall_pause(struct gk20a *g);
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void mc_gp10b_intr_nonstall_resume(struct gk20a *g);
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void mc_gp10b_ltc_isr(struct gk20a *g);
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#ifdef CONFIG_NVGPU_HAL_NON_FUSA
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void mc_gp10b_intr_enable(struct gk20a *g);
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#endif
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#endif
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