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1c40d09c4c
bug 1648908 This commit adds support for FECS ctxsw tracing. Code is compiled conditionnaly under CONFIG_GK20_CTXSW_TRACE. This feature requires an updated FECS ucode that writes one record to a ring buffer on each context switch. On RM/Kernel side, the GPU driver reads records from the master ring buffer and generates trace entries into a user-facing VM ring buffer. For each record in the master ring buffer, RM/Kernel has to retrieve the vmid+pid of the user process that submitted related work. Features currently implemented: - master ring buffer allocation - debugfs to dump master ring buffer - FECS record per context switch (with both current and new contexts) - dedicated device for ctxsw tracing (access to VM ring buffer) - SOF generation (and access to PTIMER) - VM ring buffer allocation, and reconfiguration - enable/disable tracing at user level - event-based trace filtering - context_ptr to vmid+pid mapping - read system call for ctxsw dev - mmap system call for ctxsw dev (direct access to VM ring buffer) - poll system call for ctxsw dev - save/restore register on ELPG/CG6 - separate user ring from FECS ring handling Features requiring ucode changes: - enable/disable tracing at FECS level - actual busy time on engine (bug 1642354) - master ring buffer threshold interrupt (P1) - API for GPU to CPU timestamp conversion (P1) - vmid/pid/uid based filtering (P1) Change-Id: I8e39c648221ee0fa09d5df8524b03dca83fe24f3 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1022737 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
83 lines
2.2 KiB
C
83 lines
2.2 KiB
C
/*
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* drivers/video/tegra/host/gk20a/hal_gk20a.c
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*
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* GK20A Tegra HAL interface.
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*
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* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "hal_gk20a.h"
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#include "ltc_gk20a.h"
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#include "fb_gk20a.h"
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#include "gk20a.h"
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#include "gk20a_gating_reglist.h"
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#include "channel_gk20a.h"
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#include "gr_ctx_gk20a.h"
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#include "fecs_trace_gk20a.h"
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#include "mm_gk20a.h"
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#include "mc_gk20a.h"
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#include "pmu_gk20a.h"
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#include "clk_gk20a.h"
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#include "regops_gk20a.h"
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#include "therm_gk20a.h"
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static struct gpu_ops gk20a_ops = {
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.clock_gating = {
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.slcg_gr_load_gating_prod =
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gr_gk20a_slcg_gr_load_gating_prod,
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.slcg_perf_load_gating_prod =
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gr_gk20a_slcg_perf_load_gating_prod,
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.slcg_ltc_load_gating_prod =
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ltc_gk20a_slcg_ltc_load_gating_prod,
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.blcg_gr_load_gating_prod =
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gr_gk20a_blcg_gr_load_gating_prod,
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.pg_gr_load_gating_prod =
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gr_gk20a_pg_gr_load_gating_prod,
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.slcg_therm_load_gating_prod =
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gr_gk20a_slcg_therm_load_gating_prod,
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},
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};
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int gk20a_init_hal(struct gk20a *g)
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{
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struct gpu_ops *gops = &g->ops;
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struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
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*gops = gk20a_ops;
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gops->privsecurity = 0;
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gops->securegpccs = 0;
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gk20a_init_mc(gops);
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gk20a_init_ltc(gops);
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gk20a_init_gr_ops(gops);
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gk20a_init_fecs_trace_ops(gops);
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gk20a_init_fb(gops);
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gk20a_init_fifo(gops);
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gk20a_init_ce2(gops);
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gk20a_init_gr_ctx(gops);
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gk20a_init_mm(gops);
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gk20a_init_pmu_ops(gops);
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gk20a_init_clk_ops(gops);
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gk20a_init_regops(gops);
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gk20a_init_debug_ops(gops);
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gk20a_init_therm_ops(gops);
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gops->name = "gk20a";
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c->twod_class = FERMI_TWOD_A;
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c->threed_class = KEPLER_C;
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c->compute_class = KEPLER_COMPUTE_A;
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c->gpfifo_class = KEPLER_CHANNEL_GPFIFO_C;
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c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_A;
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c->dma_copy_class = KEPLER_DMA_COPY_A;
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return 0;
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}
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