mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 01:50:07 +03:00
2eb6dcb469
Implement support for 64kB large page size. Add an API to create an address space via IOCTL so that we can accept flags, and assign one flag for enabling 64kB large page size. Also adds APIs to set per-context large page size. This is possible only on Maxwell, so return error if caller tries to set large page size on Kepler. Default large page size is still 128kB. Change-Id: I20b51c8f6d4a984acae8411ace3de9000c78e82f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
547 lines
13 KiB
C
547 lines
13 KiB
C
/*
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* drivers/video/tegra/host/gk20a/platform_gk20a_tegra.c
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*
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* GK20A Tegra Platform Interface
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*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/of_platform.h>
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#include <linux/nvhost.h>
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#include <linux/debugfs.h>
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#include <linux/tegra-powergate.h>
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#include <linux/platform_data/tegra_edp.h>
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#include <uapi/linux/nvgpu.h>
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#include <linux/dma-buf.h>
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#include <linux/nvmap.h>
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#include <linux/tegra_pm_domains.h>
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#include "gk20a.h"
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#include "hal_gk20a.h"
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#include "platform_gk20a.h"
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#include "gk20a_scale.h"
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#define TEGRA_GK20A_BW_PER_FREQ 32
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#define TEGRA_GM20B_BW_PER_FREQ 64
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#define TEGRA_DDR3_BW_PER_FREQ 16
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#define TEGRA_DDR4_BW_PER_FREQ 16
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extern struct device tegra_vpr_dev;
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struct gk20a_platform t132_gk20a_tegra_platform;
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struct gk20a_emc_params {
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long bw_ratio;
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};
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#define MHZ_TO_HZ(x) ((x) * 1000000)
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#define HZ_TO_MHZ(x) ((x) / 1000000)
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static void gk20a_tegra_secure_page_destroy(struct platform_device *pdev,
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struct secure_page_buffer *secure_buffer)
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{
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dma_free_attrs(&tegra_vpr_dev, secure_buffer->size,
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(void *)(uintptr_t)secure_buffer->iova,
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secure_buffer->iova, &secure_buffer->attrs);
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}
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static int gk20a_tegra_secure_page_alloc(struct platform_device *pdev)
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{
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struct gk20a_platform *platform = platform_get_drvdata(pdev);
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struct secure_page_buffer *secure_buffer = &platform->secure_buffer;
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DEFINE_DMA_ATTRS(attrs);
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dma_addr_t iova;
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size_t size = PAGE_SIZE;
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(void)dma_alloc_attrs(&tegra_vpr_dev, size, &iova,
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DMA_MEMORY_NOMAP, &attrs);
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if (dma_mapping_error(&tegra_vpr_dev, iova))
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return -ENOMEM;
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secure_buffer->size = size;
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secure_buffer->iova = iova;
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secure_buffer->attrs = attrs;
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secure_buffer->destroy = gk20a_tegra_secure_page_destroy;
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return 0;
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}
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static void gk20a_tegra_secure_destroy(struct platform_device *pdev,
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struct gr_ctx_buffer_desc *desc)
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{
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gk20a_free_sgtable(&desc->sgt);
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dma_free_attrs(&tegra_vpr_dev, desc->size,
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(void *)(uintptr_t)desc->iova,
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desc->iova, &desc->attrs);
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}
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static int gk20a_tegra_secure_alloc(struct platform_device *pdev,
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struct gr_ctx_buffer_desc *desc,
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size_t size)
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{
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struct gk20a_platform *platform = platform_get_drvdata(pdev);
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struct device *dev = &pdev->dev;
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DEFINE_DMA_ATTRS(attrs);
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dma_addr_t iova;
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struct sg_table *sgt;
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struct page *page;
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int err = 0;
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if (!platform->secure_alloc_ready)
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return -EINVAL;
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(void)dma_alloc_attrs(&tegra_vpr_dev, size, &iova,
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DMA_MEMORY_NOMAP, &attrs);
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if (dma_mapping_error(&tegra_vpr_dev, iova))
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return -ENOMEM;
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desc->iova = iova;
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desc->size = size;
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desc->attrs = attrs;
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desc->destroy = gk20a_tegra_secure_destroy;
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sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
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if (!sgt) {
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gk20a_err(dev, "failed to allocate memory\n");
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goto fail;
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}
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err = sg_alloc_table(sgt, 1, GFP_KERNEL);
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if (err) {
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gk20a_err(dev, "failed to allocate sg_table\n");
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goto fail_sgt;
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}
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page = phys_to_page(iova);
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sg_set_page(sgt->sgl, page, size, 0);
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sg_dma_address(sgt->sgl) = iova;
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desc->sgt = sgt;
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return err;
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fail_sgt:
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kfree(sgt);
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fail:
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dma_free_attrs(&tegra_vpr_dev, desc->size,
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(void *)(uintptr_t)&desc->iova,
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desc->iova, &desc->attrs);
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return err;
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}
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/*
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* gk20a_tegra_get_emc_rate()
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*
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* This function returns the minimum emc clock based on gpu frequency
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*/
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long gk20a_tegra_get_emc_rate(struct gk20a *g,
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struct gk20a_emc_params *emc_params, long freq)
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{
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long hz;
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freq = HZ_TO_MHZ(freq);
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hz = (freq * emc_params->bw_ratio);
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hz = (hz * min(g->pmu.load_avg, g->emc3d_ratio)) / 1000;
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hz = MHZ_TO_HZ(hz);
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return hz;
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}
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/*
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* gk20a_tegra_postscale(profile, freq)
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*
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* This function sets emc frequency based on current gpu frequency
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*/
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static void gk20a_tegra_postscale(struct platform_device *pdev,
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unsigned long freq)
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{
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struct gk20a_platform *platform = platform_get_drvdata(pdev);
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struct gk20a_scale_profile *profile = platform->g->scale_profile;
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struct gk20a_emc_params *emc_params = profile->private_data;
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struct gk20a *g = get_gk20a(pdev);
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long after = gk20a_clk_get_rate(g);
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long emc_target = gk20a_tegra_get_emc_rate(g, emc_params, after);
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clk_set_rate(platform->clk[2], emc_target);
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}
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/*
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* gk20a_tegra_prescale(profile, freq)
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*
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* This function informs EDP about changed constraints.
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*/
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static void gk20a_tegra_prescale(struct platform_device *pdev)
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{
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struct gk20a *g = get_gk20a(pdev);
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u32 avg = 0;
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gk20a_pmu_load_norm(g, &avg);
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tegra_edp_notify_gpu_load(avg, gk20a_clk_get_rate(g));
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}
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/*
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* gk20a_tegra_calibrate_emc()
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*
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*/
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void gk20a_tegra_calibrate_emc(struct platform_device *pdev,
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struct gk20a_emc_params *emc_params)
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{
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enum tegra_chipid cid = tegra_get_chipid();
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long gpu_bw, emc_bw;
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/* store gpu bw based on soc */
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switch (cid) {
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case TEGRA_CHIPID_TEGRA21:
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gpu_bw = TEGRA_GM20B_BW_PER_FREQ;
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break;
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case TEGRA_CHIPID_TEGRA12:
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case TEGRA_CHIPID_TEGRA13:
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gpu_bw = TEGRA_GK20A_BW_PER_FREQ;
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break;
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case TEGRA_CHIPID_UNKNOWN:
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default:
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gpu_bw = 0;
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break;
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}
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/* TODO detect DDR type.
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* Okay for now since DDR3 and DDR4 have the same BW ratio */
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emc_bw = TEGRA_DDR3_BW_PER_FREQ;
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/* Calculate the bandwidth ratio of gpu_freq <-> emc_freq
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* NOTE the ratio must come out as an integer */
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emc_params->bw_ratio = (gpu_bw / emc_bw);
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}
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/*
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* gk20a_tegra_is_railgated()
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*
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* Check status of gk20a power rail
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*/
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static bool gk20a_tegra_is_railgated(struct platform_device *pdev)
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{
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bool ret = false;
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if (!tegra_platform_is_linsim())
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ret = !tegra_powergate_is_powered(TEGRA_POWERGATE_GPU);
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return ret;
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}
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/*
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* gk20a_tegra_railgate()
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*
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* Gate (disable) gk20a power rail
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*/
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static int gk20a_tegra_railgate(struct platform_device *pdev)
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{
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if (!tegra_platform_is_linsim() &&
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tegra_powergate_is_powered(TEGRA_POWERGATE_GPU))
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tegra_powergate_partition(TEGRA_POWERGATE_GPU);
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return 0;
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}
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/*
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* gk20a_tegra_unrailgate()
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*
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* Ungate (enable) gk20a power rail
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*/
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static int gk20a_tegra_unrailgate(struct platform_device *pdev)
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{
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int ret = 0;
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if (!tegra_platform_is_linsim())
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ret = tegra_unpowergate_partition(TEGRA_POWERGATE_GPU);
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return ret;
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}
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struct {
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char *name;
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unsigned long default_rate;
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} tegra_gk20a_clocks[] = {
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{"PLLG_ref", UINT_MAX},
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{"pwr", 204000000},
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{"emc", UINT_MAX} };
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/*
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* gk20a_tegra_get_clocks()
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*
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* This function finds clocks in tegra platform and populates
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* the clock information to gk20a platform data.
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*/
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static int gk20a_tegra_get_clocks(struct platform_device *pdev)
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{
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struct gk20a_platform *platform = platform_get_drvdata(pdev);
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char devname[16];
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int i;
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int ret = 0;
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snprintf(devname, sizeof(devname),
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(pdev->id <= 0) ? "tegra_%s" : "tegra_%s.%d\n",
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pdev->name, pdev->id);
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platform->num_clks = 0;
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for (i = 0; i < ARRAY_SIZE(tegra_gk20a_clocks); i++) {
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long rate = tegra_gk20a_clocks[i].default_rate;
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struct clk *c;
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c = clk_get_sys(devname, tegra_gk20a_clocks[i].name);
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if (IS_ERR(c)) {
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ret = PTR_ERR(c);
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goto err_get_clock;
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}
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rate = clk_round_rate(c, rate);
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clk_set_rate(c, rate);
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platform->clk[i] = c;
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}
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platform->num_clks = i;
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return 0;
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err_get_clock:
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while (i--)
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clk_put(platform->clk[i]);
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return ret;
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}
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static void gk20a_tegra_scale_init(struct platform_device *pdev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(pdev);
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struct gk20a_scale_profile *profile = platform->g->scale_profile;
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struct gk20a_emc_params *emc_params;
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if (!profile)
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return;
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emc_params = kzalloc(sizeof(*emc_params), GFP_KERNEL);
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if (!emc_params)
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return;
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gk20a_tegra_calibrate_emc(pdev, emc_params);
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profile->private_data = emc_params;
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}
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static void gk20a_tegra_debug_dump(struct platform_device *pdev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(pdev);
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struct gk20a *g = platform->g;
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nvhost_debug_dump_device(g->host1x_dev);
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}
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static int gk20a_tegra_busy(struct platform_device *dev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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struct gk20a *g = platform->g;
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if (g->host1x_dev)
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return nvhost_module_busy_ext(g->host1x_dev);
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return 0;
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}
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static void gk20a_tegra_idle(struct platform_device *dev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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struct gk20a *g = platform->g;
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if (g->host1x_dev)
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nvhost_module_idle_ext(g->host1x_dev);
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}
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static int gk20a_tegra_probe(struct platform_device *dev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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struct device_node *np = dev->dev.of_node;
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const __be32 *host1x_ptr;
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struct platform_device *host1x_pdev = NULL;
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host1x_ptr = of_get_property(np, "nvidia,host1x", NULL);
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if (host1x_ptr) {
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struct device_node *host1x_node =
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of_find_node_by_phandle(be32_to_cpup(host1x_ptr));
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host1x_pdev = of_find_device_by_node(host1x_node);
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if (!host1x_pdev) {
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dev_warn(&dev->dev, "host1x device not available");
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return -EPROBE_DEFER;
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}
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} else {
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host1x_pdev = to_platform_device(dev->dev.parent);
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dev_warn(&dev->dev, "host1x reference not found. assuming host1x to be parent");
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}
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platform->g->host1x_dev = host1x_pdev;
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if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA13) {
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t132_gk20a_tegra_platform.g = platform->g;
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*platform = t132_gk20a_tegra_platform;
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}
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/* WAR for bug 1547668: Disable railgating and scaling irrespective of
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* platform data if the rework has not been made. */
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if (tegra_get_chipid() == TEGRA_CHIPID_TEGRA21) {
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np = of_find_node_by_path("/gpu-dvfs-rework");
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if (!(np && of_device_is_available(np))) {
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platform->devfreq_governor = "";
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dev_warn(&dev->dev, "board does not support scaling");
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}
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}
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gk20a_tegra_get_clocks(dev);
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return 0;
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}
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static int gk20a_tegra_late_probe(struct platform_device *dev)
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{
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struct gk20a_platform *platform = gk20a_get_platform(dev);
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/* Make gk20a power domain a subdomain of host1x */
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nvhost_register_client_domain(&platform->g->pd);
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/* Initialise tegra specific scaling quirks */
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gk20a_tegra_scale_init(dev);
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return 0;
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}
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static int gk20a_tegra_suspend(struct device *dev)
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{
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tegra_edp_notify_gpu_load(0, 0);
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return 0;
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}
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struct gk20a_platform t132_gk20a_tegra_platform = {
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.has_syncpoints = true,
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/* power management configuration */
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.railgate_delay = 500,
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.clockgate_delay = 50,
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.can_railgate = true,
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.enable_slcg = true,
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.enable_blcg = true,
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.enable_elcg = true,
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.enable_elpg = true,
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.enable_aelpg = true,
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.default_big_page_size = SZ_128K,
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.probe = gk20a_tegra_probe,
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.late_probe = gk20a_tegra_late_probe,
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/* power management callbacks */
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.suspend = gk20a_tegra_suspend,
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.railgate = gk20a_tegra_railgate,
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.unrailgate = gk20a_tegra_unrailgate,
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.is_railgated = gk20a_tegra_is_railgated,
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.busy = gk20a_tegra_busy,
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.idle = gk20a_tegra_idle,
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/* frequency scaling configuration */
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.prescale = gk20a_tegra_prescale,
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.postscale = gk20a_tegra_postscale,
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.devfreq_governor = "nvhost_podgov",
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.qos_id = PM_QOS_GPU_FREQ_MIN,
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.secure_alloc = gk20a_tegra_secure_alloc,
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.secure_page_alloc = gk20a_tegra_secure_page_alloc,
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.dump_platform_dependencies = gk20a_tegra_debug_dump,
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};
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struct gk20a_platform gk20a_tegra_platform = {
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.has_syncpoints = true,
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/* power management configuration */
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.railgate_delay = 500,
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.clockgate_delay = 50,
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.can_railgate = true,
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.enable_slcg = true,
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.enable_blcg = true,
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.enable_elcg = true,
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.enable_elpg = true,
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.enable_aelpg = true,
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.default_big_page_size = SZ_128K,
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.probe = gk20a_tegra_probe,
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.late_probe = gk20a_tegra_late_probe,
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/* power management callbacks */
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.suspend = gk20a_tegra_suspend,
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.railgate = gk20a_tegra_railgate,
|
|
.unrailgate = gk20a_tegra_unrailgate,
|
|
.is_railgated = gk20a_tegra_is_railgated,
|
|
|
|
.busy = gk20a_tegra_busy,
|
|
.idle = gk20a_tegra_idle,
|
|
|
|
/* frequency scaling configuration */
|
|
.prescale = gk20a_tegra_prescale,
|
|
.postscale = gk20a_tegra_postscale,
|
|
.devfreq_governor = "nvhost_podgov",
|
|
.qos_id = PM_QOS_GPU_FREQ_MIN,
|
|
|
|
.secure_alloc = gk20a_tegra_secure_alloc,
|
|
.secure_page_alloc = gk20a_tegra_secure_page_alloc,
|
|
.dump_platform_dependencies = gk20a_tegra_debug_dump,
|
|
};
|
|
|
|
struct gk20a_platform gm20b_tegra_platform = {
|
|
.has_syncpoints = true,
|
|
|
|
/* power management configuration */
|
|
.railgate_delay = INT_MAX,
|
|
.clockgate_delay = 50,
|
|
/* Disable all power features for gm20b */
|
|
.can_railgate = true,
|
|
.enable_slcg = true,
|
|
.enable_blcg = true,
|
|
.enable_elcg = true,
|
|
.enable_elpg = true,
|
|
.enable_aelpg = true,
|
|
|
|
.default_big_page_size = SZ_128K,
|
|
|
|
.probe = gk20a_tegra_probe,
|
|
.late_probe = gk20a_tegra_late_probe,
|
|
|
|
/* power management callbacks */
|
|
.suspend = gk20a_tegra_suspend,
|
|
.railgate = gk20a_tegra_railgate,
|
|
.unrailgate = gk20a_tegra_unrailgate,
|
|
.is_railgated = gk20a_tegra_is_railgated,
|
|
|
|
.busy = gk20a_tegra_busy,
|
|
.idle = gk20a_tegra_idle,
|
|
|
|
/* frequency scaling configuration */
|
|
.prescale = gk20a_tegra_prescale,
|
|
.postscale = gk20a_tegra_postscale,
|
|
.devfreq_governor = "nvhost_podgov",
|
|
.qos_id = PM_QOS_GPU_FREQ_MIN,
|
|
|
|
.secure_alloc = gk20a_tegra_secure_alloc,
|
|
.secure_page_alloc = gk20a_tegra_secure_page_alloc,
|
|
.dump_platform_dependencies = gk20a_tegra_debug_dump,
|
|
};
|