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1ce899ce46
Preparing to push hvrtos gpu server changes which requires bellow CFLAGS:
-Werror -Wall -Wextra \
-Wmissing-braces -Wpointer-arith -Wundef \
-Wconversion -Wsign-conversion \
-Wformat-security \
-Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough
Jira GVSCI-11640
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I25167f17f231ed741f19af87ca0aa72991563a0f
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2653746
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
71 lines
2.3 KiB
C
71 lines
2.3 KiB
C
/*
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* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/log.h>
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#include <nvgpu/bitops.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/dma.h>
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#include <nvgpu/io.h>
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#include <nvgpu/hw_sim.h>
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#include <nvgpu/sim.h>
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#include <nvgpu/utils.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/string.h>
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#include "sim_ga10b.h"
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#ifdef CONFIG_NVGPU_SIM
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static void nvgpu_sim_esc_readl_ga10b(struct gk20a *g,
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const char *path, u32 index, u32 *data)
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{
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int err;
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u32 data_offset;
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sim_write_hdr(g, sim_msg_function_sim_escape_read_v(),
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sim_escape_read_hdr_size());
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*sim_msg_param(g, 0) = index;
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*sim_msg_param(g, 4) = sizeof(u32);
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data_offset = (u32)round_up(
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nvgpu_safe_add_u64(strlen(path), 1ULL), sizeof(u32));
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*sim_msg_param(g, 8) = data_offset;
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strcpy((char *)sim_msg_param(g, sim_escape_read_hdr_size()), path);
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err = issue_rpc_and_wait(g);
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if (err == 0) {
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nvgpu_memcpy((u8 *)data, (u8 *)sim_msg_param(g,
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nvgpu_safe_add_u32(data_offset,
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sim_escape_read_hdr_size())),
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sizeof(u32));
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} else {
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*data = 0xffffffff;
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WARN(1, "issue_rpc_and_wait failed err=%d", err);
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}
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}
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void nvgpu_init_sim_support_ga10b(struct gk20a *g)
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{
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if (g->sim) {
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g->sim->esc_readl = nvgpu_sim_esc_readl_ga10b;
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}
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}
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#endif /* CONFIG_NVGPU_SIM */
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