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1ce899ce46
Preparing to push hvrtos gpu server changes which requires bellow CFLAGS:
-Werror -Wall -Wextra \
-Wmissing-braces -Wpointer-arith -Wundef \
-Wconversion -Wsign-conversion \
-Wformat-security \
-Wmissing-declarations -Wredundant-decls -Wimplicit-fallthrough
Jira GVSCI-11640
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I25167f17f231ed741f19af87ca0aa72991563a0f
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2653746
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
184 lines
6.4 KiB
C
184 lines
6.4 KiB
C
/*
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* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PMU_PG_H
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#define NVGPU_PMU_PG_H
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#include <nvgpu/lock.h>
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#include <nvgpu/cond.h>
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#include <nvgpu/thread.h>
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#include <nvgpu/nvgpu_common.h>
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#include <nvgpu/flcnif_cmn.h>
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#include <nvgpu/pmu/pmuif/nvgpu_cmdif.h>
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#include <nvgpu/pmu/pmuif/pg.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/atomic.h>
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#include <include/nvgpu/pmu.h>
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struct nvgpu_pmu;
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struct vm_gk20a;
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struct pmu_pg_stats_data;
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struct rpc_handler_payload;
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/*PG defines used by nvpgu-pmu*/
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#define PMU_PG_SEQ_BUF_SIZE 4096U
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#define PMU_PG_IDLE_THRESHOLD_SIM 1000U
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#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD_SIM 4000000U
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/* TBD: QT or else ? */
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#define PMU_PG_IDLE_THRESHOLD 15000U
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#define PMU_PG_POST_POWERUP_IDLE_THRESHOLD 1000000U
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#define PMU_PG_LPWR_FEATURE_RPPG 0x0U
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#define PMU_PG_LPWR_FEATURE_MSCG 0x1U
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#define PMU_MSCG_DISABLED 0U
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#define PMU_MSCG_ENABLED 1U
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/* Default Sampling Period of AELPG */
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#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000U)
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/* Default values of APCTRL parameters */
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#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100U)
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#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000U)
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#define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000U)
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#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200U)
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/* State of golden image */
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enum {
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GOLDEN_IMG_NOT_READY = 0,
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GOLDEN_IMG_SUSPEND,
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GOLDEN_IMG_READY,
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};
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struct nvgpu_pg_init {
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bool state_change;
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bool state_destroy;
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struct nvgpu_cond wq;
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struct nvgpu_thread state_task;
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};
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struct nvgpu_pmu_pg {
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u32 elpg_stat;
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u32 disallow_state;
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u32 elpg_ms_stat;
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#define PMU_ELPG_ENABLE_ALLOW_DELAY_MSEC 1U /* msec */
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struct nvgpu_pg_init pg_init;
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struct nvgpu_mutex pg_mutex; /* protect pg-RPPG/MSCG enable/disable */
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struct nvgpu_mutex elpg_mutex; /* protect elpg enable/disable */
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struct nvgpu_mutex elpg_ms_mutex; /* protect elpg_ms enable/disable */
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/* disable -1, enable +1, <=0 elpg disabled, > 0 elpg enabled */
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int elpg_refcnt;
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int elpg_ms_refcnt;
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u32 aelpg_param[5];
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bool zbc_ready;
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bool zbc_save_done;
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bool buf_loaded;
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struct nvgpu_mem pg_buf;
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bool initialized;
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u32 stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE];
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struct nvgpu_mem seq_buf;
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nvgpu_atomic_t golden_image_initialized;
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u32 mscg_stat;
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u32 mscg_transition_state;
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int (*elpg_statistics)(struct gk20a *g, u32 pg_engine_id,
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struct pmu_pg_stats_data *pg_stat_data);
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int (*init_param)(struct gk20a *g, u32 pg_engine_id);
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int (*set_sub_feature_mask)(struct gk20a *g,
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u32 pg_engine_id);
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u32 (*supported_engines_list)(struct gk20a *g);
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u32 (*engines_feature_list)(struct gk20a *g,
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u32 pg_engine_id);
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bool (*is_lpwr_feature_supported)(struct gk20a *g,
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u32 feature_id);
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int (*lpwr_enable_pg)(struct gk20a *g, bool pstate_lock);
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int (*lpwr_disable_pg)(struct gk20a *g, bool pstate_lock);
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int (*param_post_init)(struct gk20a *g);
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void (*save_zbc)(struct gk20a *g, u32 entries);
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/* ELPG cmd post functions */
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int (*allow)(struct gk20a *g, struct nvgpu_pmu *pmu,
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u8 pg_engine_id);
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int (*disallow)(struct gk20a *g, struct nvgpu_pmu *pmu,
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u8 pg_engine_id);
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int (*init)(struct gk20a *g, struct nvgpu_pmu *pmu,
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u8 pg_engine_id);
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int (*alloc_dmem)(struct gk20a *g, struct nvgpu_pmu *pmu,
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u8 pg_engine_id);
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int (*load_buff)(struct gk20a *g, struct nvgpu_pmu *pmu);
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int (*hw_load_zbc)(struct gk20a *g, struct nvgpu_pmu *pmu);
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void (*rpc_handler)(struct gk20a *g, struct nvgpu_pmu *pmu,
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struct nv_pmu_rpc_header *rpc, struct rpc_handler_payload *rpc_payload);
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int (*init_send)(struct gk20a *g, struct nvgpu_pmu *pmu, u8 pg_engine_id);
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int (*process_pg_event)(struct gk20a *g, void *pmumsg);
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};
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/*PG defines used by nvpgu-pmu*/
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struct pmu_pg_stats_data {
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u32 gating_cnt;
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u32 ingating_time;
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u32 ungating_time;
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u32 avg_entry_latency_us;
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u32 avg_exit_latency_us;
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};
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/* PG init*/
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int nvgpu_pmu_pg_init(struct gk20a *g, struct nvgpu_pmu *pmu,
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struct nvgpu_pmu_pg **pg);
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void nvgpu_pmu_pg_deinit(struct gk20a *g, struct nvgpu_pmu *pmu,
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struct nvgpu_pmu_pg *pg);
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int nvgpu_pmu_pg_sw_setup(struct gk20a *g, struct nvgpu_pmu *pmu,
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struct nvgpu_pmu_pg *pg);
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void nvgpu_pmu_pg_destroy(struct gk20a *g, struct nvgpu_pmu *pmu,
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struct nvgpu_pmu_pg *pg);
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int nvgpu_pmu_restore_golden_img_state(struct gk20a *g);
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/* PG enable/disable */
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int nvgpu_pmu_reenable_elpg(struct gk20a *g);
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int nvgpu_pmu_enable_elpg(struct gk20a *g);
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int nvgpu_pmu_disable_elpg(struct gk20a *g);
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int nvgpu_pmu_enable_elpg_ms(struct gk20a *g);
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int nvgpu_pmu_disable_elpg_ms(struct gk20a *g);
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int nvgpu_pmu_pg_global_enable(struct gk20a *g, bool enable_pg);
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int nvgpu_pmu_get_pg_stats(struct gk20a *g, u32 pg_engine_id,
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struct pmu_pg_stats_data *pg_stat_data);
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/* AELPG */
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int nvgpu_aelpg_init(struct gk20a *g);
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int nvgpu_aelpg_init_and_enable(struct gk20a *g, u8 ctrl_id);
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int nvgpu_pmu_ap_send_command(struct gk20a *g,
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union pmu_ap_cmd *p_ap_cmd, bool b_block);
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void nvgpu_pmu_set_golden_image_initialized(struct gk20a *g, u8 state);
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/* PG ops*/
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int nvgpu_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
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struct pmu_pg_stats_data *pg_stat_data);
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void nvgpu_pmu_save_zbc(struct gk20a *g, u32 entries);
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bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id);
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int nvgpu_pmu_pg_buf_alloc(struct gk20a *g, struct nvgpu_pmu *pmu, u32 size);
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u64 nvgpu_pmu_pg_buf_get_gpu_va(struct gk20a *g, struct nvgpu_pmu *pmu);
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#endif /* NVGPU_PMU_PG_H */
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