mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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1da69dd8b2
Remove the mm.get_iova_addr() HAL and replace it with a new HAL called mm.gpu_phys_addr(). This new HAL provides the real phys address that should be passed to the GPU from a physical address obtained from a scatter list. It also provides a mechanism by which the HAL code can add extra bits to a GPU physical address based on the attributes passed in. This is necessary during GMMU page table programming. Also remove the flags argument from the various address functions. This flag was used for adding an IO coherence bit to the GPU physical address which is not supported. JIRA NVGPU-30 Change-Id: I69af5b1c6bd905c4077c26c098fac101c6b41a33 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530864 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
91 lines
2.5 KiB
C
91 lines
2.5 KiB
C
/*
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* GM20B MMU
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*
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* Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "gk20a/gk20a.h"
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#include "mm_gm20b.h"
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#include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h>
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#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
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static void gm20b_mm_set_big_page_size(struct gk20a *g,
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struct nvgpu_mem *mem, int size)
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{
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u32 val;
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gk20a_dbg_fn("");
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gk20a_dbg_info("big page size %d\n", size);
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val = nvgpu_mem_rd32(g, mem, ram_in_big_page_size_w());
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val &= ~ram_in_big_page_size_m();
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if (size == SZ_64K)
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val |= ram_in_big_page_size_64kb_f();
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else
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val |= ram_in_big_page_size_128kb_f();
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nvgpu_mem_wr32(g, mem, ram_in_big_page_size_w(), val);
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gk20a_dbg_fn("done");
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}
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static u32 gm20b_mm_get_big_page_sizes(void)
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{
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return SZ_64K | SZ_128K;
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}
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static u32 gm20b_mm_get_default_big_page_size(void)
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{
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return SZ_128K;
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}
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static bool gm20b_mm_support_sparse(struct gk20a *g)
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{
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return true;
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}
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static bool gm20b_mm_is_bar1_supported(struct gk20a *g)
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{
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return true;
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}
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u64 gm20b_gpu_phys_addr(struct gk20a *g,
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struct nvgpu_gmmu_attrs *attrs, u64 phys)
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{
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return phys;
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}
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void gm20b_init_mm(struct gpu_ops *gops)
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{
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gops->mm.support_sparse = gm20b_mm_support_sparse;
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gops->mm.gmmu_map = gk20a_locked_gmmu_map;
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gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap;
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gops->mm.vm_bind_channel = gk20a_vm_bind_channel;
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gops->mm.fb_flush = gk20a_mm_fb_flush;
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gops->mm.l2_invalidate = gk20a_mm_l2_invalidate;
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gops->mm.l2_flush = gk20a_mm_l2_flush;
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gops->mm.cbc_clean = gk20a_mm_cbc_clean;
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gops->mm.set_big_page_size = gm20b_mm_set_big_page_size;
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gops->mm.get_big_page_sizes = gm20b_mm_get_big_page_sizes;
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gops->mm.get_default_big_page_size = gm20b_mm_get_default_big_page_size;
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gops->mm.gpu_phys_addr = gm20b_gpu_phys_addr;
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gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits;
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gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels;
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gops->mm.init_pdb = gk20a_mm_init_pdb;
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gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw;
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gops->mm.is_bar1_supported = gm20b_mm_is_bar1_supported;
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gops->mm.init_inst_block = gk20a_init_inst_block;
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gops->mm.mmu_fault_pending = gk20a_fifo_mmu_fault_pending;
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}
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