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9a89b94a68
After hs_ucode_bootstrap the PMU falcon registers were being checked incorrectly. Fix the logic and update the register offsets with that of GPCCS registers. JIRA NVGPU-2214 Change-Id: Ic28cd8eb6894fc16418434a95e46f81095861892 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2261166 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>