mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 18:16:01 +03:00
3d9c33c595
Add clock arbiter skeleton with support of clock sessions, notifications on clock changes, request numbering, and asynchronous handling of clock requests. Provides minimum behaviour to allow unit tests implementation. Actual arbitration and clock settings will be done separately. For now, dummy arbiter keeps last requested target mhz. Actual arbiter may move to a lockless implementation. Jira DNVGPU-125 Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: http://git-master/r/1223476 (cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461) Reviewed-on: http://git-master/r/1243105 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
59 lines
1.4 KiB
C
59 lines
1.4 KiB
C
/*
|
|
* general p state infrastructure
|
|
*
|
|
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms and conditions of the GNU General Public License,
|
|
* version 2, as published by the Free Software Foundation.
|
|
*
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
* more details.
|
|
*/
|
|
#ifndef __PSTATE_H__
|
|
#define __PSTATE_H__
|
|
|
|
#include "gk20a/gk20a.h"
|
|
#include "clk/clk.h"
|
|
|
|
#define CTRL_PERF_PSTATE_TYPE_3X 0x3
|
|
|
|
#define CTRL_PERF_PSTATE_P0 0
|
|
#define CTRL_PERF_PSTATE_P5 5
|
|
#define CTRL_PERF_PSTATE_P8 8
|
|
|
|
#define CLK_SET_INFO_MAX_SIZE (32)
|
|
|
|
struct clk_set_info {
|
|
enum nv_pmu_clk_clkwhich clkwhich;
|
|
u32 nominal_mhz;
|
|
u32 min_mhz;
|
|
u32 max_mhz;
|
|
};
|
|
|
|
struct clk_set_info_list {
|
|
u32 num_info;
|
|
struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE];
|
|
};
|
|
|
|
struct pstate {
|
|
struct boardobj super;
|
|
u32 num;
|
|
struct clk_set_info_list clklist;
|
|
};
|
|
|
|
struct pstates {
|
|
struct boardobjgrp_e32 super;
|
|
u32 num_levels;
|
|
};
|
|
|
|
int gk20a_init_pstate_support(struct gk20a *g);
|
|
int gk20a_init_pstate_pmu_support(struct gk20a *g);
|
|
|
|
struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, u32 pstate_num,
|
|
enum nv_pmu_clk_clkwhich clkwhich);
|
|
|
|
#endif /* __PSTATE_H__ */
|