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5cfd481cf5
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations caused by include guards by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER_H' JIRA NVGPU-1028 Change-Id: Ic60b2de8bb705f189134483fff1e2dff8ea96a12 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808186 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
41 lines
1.8 KiB
C
41 lines
1.8 KiB
C
/*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GM20B_MM_GM20B_H
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#define NVGPU_GM20B_MM_GM20B_H
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struct gk20a;
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#define PDE_ADDR_START(x, y) ((x) & ~((0x1UL << (y)) - 1))
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#define PDE_ADDR_END(x, y) ((x) | ((0x1UL << (y)) - 1))
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void gm20b_mm_set_big_page_size(struct gk20a *g,
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struct nvgpu_mem *mem, int size);
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u32 gm20b_mm_get_big_page_sizes(void);
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u32 gm20b_mm_get_default_big_page_size(void);
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bool gm20b_mm_support_sparse(struct gk20a *g);
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bool gm20b_mm_is_bar1_supported(struct gk20a *g);
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u64 gm20b_gpu_phys_addr(struct gk20a *g,
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struct nvgpu_gmmu_attrs *attrs, u64 phys);
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u32 gm20b_get_kind_invalid(void);
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u32 gm20b_get_kind_pitch(void);
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#endif /* NVGPU_GM20B_MM_GM20B_H */
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