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4f5bd9e633
Add clk_good and pll_lock check as a part of fmon polling. This will poll for any clock related faults at FTTI interval. Add new function to poll for vbios init completion. NVGPU-4967 Bug 2849506 Bug 200564937 Change-Id: I5bc885329981e07376824e148edabe9be4120e1c Signed-off-by: Abdul Salam <absalam@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2305782 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
42 lines
1.7 KiB
C
42 lines
1.7 KiB
C
/*
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* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef CLK_MON_TU104_H
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#define CLK_MON_TU104_H
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/**
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* FMON register types
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*/
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#define FMON_THRESHOLD_HIGH 0x0U
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#define FMON_THRESHOLD_LOW 0x1U
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#define FMON_FAULT_STATUS 0x2U
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#define FMON_FAULT_STATUS_PRIV_MASK 0x3U
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#define CLK_CLOCK_MON_REG_TYPE_COUNT 0x4U
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#define CLK_MON_BITS_PER_BYTE 0x8U
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bool nvgpu_clk_mon_check_master_fault_status(struct gk20a *g);
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int nvgpu_clk_mon_check_status(struct gk20a *g, struct
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clk_domains_mon_status_params *clk_mon_status,
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u32 domain_mask);
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bool nvgpu_clk_mon_check_clk_good(struct gk20a *g);
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bool nvgpu_clk_mon_check_pll_lock(struct gk20a *g);
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#endif /* CLK_MON_TU104_H */
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