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0194d8640e
Right now in PMU we have disabled usage of VFE cached values as we have seen failures in 5.1.3.0 release. This patch will send vfe_var dependent masks to PMU which will be used for initial invalidation of dependent VFE_VAR cached values. As a result PMU will compute the dependent VARs and cache them. NVGPU-3645 Change-Id: I814ae819d77270ac45b97cf2a32726992e6f4af3 Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2137423 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
102 lines
3.7 KiB
C
102 lines
3.7 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_BOARDOBJGRPMASK_H
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#define NVGPU_BOARDOBJGRPMASK_H
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struct ctrl_boardobjgrp_mask;
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/*
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* Board Object Group Mask super-structure.
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* Used to unify access to all BOARDOBJGRPMASK_E** child classes
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*/
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struct boardobjgrpmask {
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/* Number of bits supported by the mask */
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u8 bitcount;
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/* Number of 32-bit words required to store all @ref bitCount bits */
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u8 maskdatacount;
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/*
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* Bit-mask of used-bits within last 32-bit word. Used to
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* normalize data
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*/
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u32 lastmaskfilter;
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/*
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* Start of the array of 32-bit words representing the bit-mask
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* Must be the last element of the structure.
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*/
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u32 data[CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE];
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};
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struct boardobjgrpmask_e32 {
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/*
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* BOARDOBJGRPMASK super-class. Must be the first element of the
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* structure.
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*/
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struct boardobjgrpmask super;
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/*u32 data_e32[1]; */
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};
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struct boardobjgrpmask_e255 {
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/*
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* BOARDOBJGRPMASK super-class. Must be the first element of the
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* structure.
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*/
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struct boardobjgrpmask super;
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u32 data_e255[254];
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};
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/* Init and I/O operations.*/
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int nvgpu_boardobjgrpmask_init(struct boardobjgrpmask *mask, u8 bitsize,
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struct ctrl_boardobjgrp_mask *extmask);
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int nvgpu_boardobjgrpmask_export(struct boardobjgrpmask *mask, u8 bitsize,
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struct ctrl_boardobjgrp_mask *extmask);
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/* Operations on all bits of a single mask.*/
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u8 nvgpu_boardobjgrpmask_bit_set_count(struct boardobjgrpmask *mask);
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u8 nvgpu_boardobjgrpmask_bit_idx_highest(struct boardobjgrpmask *mask);
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/* Operations on a single bit of a single mask */
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int nvgpu_boardobjgrpmask_bit_clr(struct boardobjgrpmask *mask, u8 bitidx);
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int nvgpu_boardobjgrpmask_bit_set(struct boardobjgrpmask *mask, u8 bitidx);
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bool nvgpu_boardobjgrpmask_bit_get(struct boardobjgrpmask *mask, u8 bitidx);
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int nvgpu_boardobjmask_or(struct boardobjgrpmask *dst,
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struct boardobjgrpmask *mask1, struct boardobjgrpmask *mask2);
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int nvgpu_boardobjmask_and(struct boardobjgrpmask *dst,
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struct boardobjgrpmask *mask1, struct boardobjgrpmask *mask2);
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/* Special interfaces */
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bool nvgpu_boardobjgrpmask_sizeeq(struct boardobjgrpmask *op1,
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struct boardobjgrpmask *op2);
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/* init boardobjgrpmask_e32 structure */
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#define boardobjgrpmask_e32_init(pmaske32, pextmask) \
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nvgpu_boardobjgrpmask_init(&(pmaske32)->super, \
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CTRL_BOARDOBJGRP_E32_MAX_OBJECTS, (pextmask))
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/* init boardobjgrpmask_e255 structure */
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#define boardobjgrpmask_e255_init(pmaske255, pextmask) \
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nvgpu_boardobjgrpmask_init(&(pmaske255)->super, \
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CTRL_BOARDOBJGRP_E255_MAX_OBJECTS, (pextmask))
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#endif /* NVGPU_BOARDOBJGRPMASK_H */
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