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2d9b839f21
Set safe state and get syncpt address in the kernel submission tracking syncs was implemented for userspace syncs. Now that it's clear that the user sync object provides them, there are no users left for these APIs. Remove them. Jira NVGPU-4548 Change-Id: I58e04162dee55bb8d8547c9252033f40ed908144 Signed-off-by: Konsta Hölttä <kholtta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321950 (cherry picked from commit a95c8f7ace562a11ca235d71496d3a7ce150bc7d) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2324251 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
127 lines
4.4 KiB
C
127 lines
4.4 KiB
C
/*
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*
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* Nvgpu Channel Synchronization Abstraction
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*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_CHANNEL_SYNC_H
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#define NVGPU_CHANNEL_SYNC_H
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#include <nvgpu/atomic.h>
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struct nvgpu_channel_sync;
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#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
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struct priv_cmd_entry;
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struct nvgpu_channel;
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struct nvgpu_fence_type;
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struct gk20a;
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/* Public APIS for channel_sync below */
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/*
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* Generate a gpu wait cmdbuf from sync fd.
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* Returns a gpu cmdbuf that performs the wait when executed
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*/
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int nvgpu_channel_sync_wait_fence_fd(struct nvgpu_channel_sync *s, int fd,
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struct priv_cmd_entry *entry, u32 max_wait_cmds);
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/*
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* Increment syncpoint/semaphore.
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* Returns
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* - a gpu cmdbuf that performs the increment when executed,
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* - a fence that can be passed to wait_cpu() and is_expired().
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*/
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int nvgpu_channel_sync_incr(struct nvgpu_channel_sync *s,
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struct priv_cmd_entry *entry, struct nvgpu_fence_type *fence,
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bool need_sync_fence, bool register_irq);
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/*
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* Increment syncpoint/semaphore, so that the returned fence represents
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* work completion (may need wfi) and can be returned to user space.
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* Returns
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* - a gpu cmdbuf that performs the increment when executed,
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* - a fence that can be passed to wait_cpu() and is_expired(),
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* - a nvgpu_fence_type that signals when the incr has happened.
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*/
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int nvgpu_channel_sync_incr_user(struct nvgpu_channel_sync *s,
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int wait_fence_fd, struct priv_cmd_entry *entry,
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struct nvgpu_fence_type *fence, bool wfi, bool need_sync_fence,
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bool register_irq);
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/*
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* Reset the channel syncpoint/semaphore. Syncpoint increments generally
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* wrap around the range of integer values. Current max value encompasses
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* all jobs tracked by the channel. In order to reset the syncpoint,
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* the min_value is advanced and set to the global max. Similarly,
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* for semaphores.
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*/
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void nvgpu_channel_sync_set_min_eq_max(struct nvgpu_channel_sync *s);
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/*
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* Increment the usage_counter for this instance.
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*/
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void nvgpu_channel_sync_get_ref(struct nvgpu_channel_sync *s);
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/*
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* Decrement the usage_counter for this instance and return if equals 0.
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*/
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bool nvgpu_channel_sync_put_ref_and_check(struct nvgpu_channel_sync *s);
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#endif /* CONFIG_NVGPU_KERNEL_MODE_SUBMIT */
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/**
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* @brief Free channel syncpoint/semaphore
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*
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* @param sync [in] Pointer to syncpoint/semaphore.
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*
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* Free the resources allocated by nvgpu_channel_sync_create.
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*/
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void nvgpu_channel_sync_destroy(struct nvgpu_channel_sync *sync);
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/**
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* @brief Create channel syncpoint/semaphore
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*
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* @param c [in] Pointer to Channel.
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*
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* Construct a channel_sync backed by either a syncpoint or a semaphore.
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* A channel_sync is by default constructed as backed by a syncpoint
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* if CONFIG_TEGRA_GK20A_NVHOST is defined, otherwise the channel_sync
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* is constructed as backed by a semaphore.
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*
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* @return Pointer to nvgpu_channel_sync in case of success, or NULL
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* in case of failure.
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*/
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struct nvgpu_channel_sync *nvgpu_channel_sync_create(struct nvgpu_channel *c);
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/**
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* @brief Check if OS fence framwework is needed
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*
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* @param g [in] Pointer to GPU
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*
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* Sync framework requires deferred job cleanup, wrapping syncs in FDs,
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* and other heavy stuff, which prevents deterministic submits.
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*
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* @return True is OS fence framework is needed.
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*/
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bool nvgpu_channel_sync_needs_os_fence_framework(struct gk20a *g);
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#endif /* NVGPU_CHANNEL_SYNC_H */
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