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JIRA NVGPU-5222 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Change-Id: I3004fcfd9cf17b81c6d218954da140982a76c6fd Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2316212 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
406 lines
12 KiB
C
406 lines
12 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GOPS_FB_H
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#define NVGPU_GOPS_FB_H
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#include <nvgpu/types.h>
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/**
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* @file
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*
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* common.fb interface.
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*/
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struct gk20a;
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/**
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* common.fb intr subunit hal operations.
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*
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* This structure stores common.fb interrupt subunit hal pointers.
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*
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* @see gpu_ops
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*/
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struct gops_fb_intr {
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/**
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* @brief Enable fb hub interrupts.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function enable the stalling interrupt for fb unit at MC level.
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* This function enables following fb hub interrupts.
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* MMU_ECC_UNCORRECTED_ERROR_NOTIFY: Uncorrected ECC errors.
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* MMU_NONREPLAYABLE_FAULT_NOTIFY: non-replayable fault happened.
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* MMU_NONREPLAYABLE_FAULT_OVERFLOW : non-replayable fault buffer
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* overflow occurred.
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* MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU.
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*/
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void (*enable)(struct gk20a *g);
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/**
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* @brief Disable fb hub interrupts.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function disables fb hub interrupts enabled in enable.
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* This function disables the stalling interrupt for fb unit at
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* MC level.
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*/
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void (*disable)(struct gk20a *g);
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/**
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* @brief ISR for fb hub interrupts.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This is the entry point to handle fb hub interrupts. This function
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* handled all the interrupts enabled in enable function.
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*/
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void (*isr)(struct gk20a *g);
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/**
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* @brief Checks any mmu fault interrupt is pending
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function checks and returns information about mmu fault pending.
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*
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* @return true in case of mmu faults pending, false otherwise.
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*/
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bool (*is_mmu_fault_pending)(struct gk20a *g);
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};
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/**
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* common.fb unit hal operations.
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*
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* This structure stores common.fb unit hal pointers.
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*
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* @see gpu_ops
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*/
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struct gops_fb {
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/**
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* @brief Initialize FB unit ECC support.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function allocates memory to track the ecc error counts
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* for FB unit.
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*
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* @return 0 in case of success, < 0 in case of failure.
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*/
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int (*fb_ecc_init)(struct gk20a *g);
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/**
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* @brief Free FB unit ECC support.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function deallocates memory allocated for ecc error counts
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* for FB unit.
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*/
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void (*fb_ecc_free)(struct gk20a *g);
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/**
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* @brief Initializes frame buffer h/w configuration.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* Frame Buffer(FB) init h/w function:
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* - configures address that is used for issuing flush reads to
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system memory.
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* - initializes mmu debugger buffer.
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* - enables fb unit stalling interrupt at MC level.
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* - enables fb interrupts related to mmu faults.
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*/
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void (*init_hw)(struct gk20a *g);
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/**
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* @brief Intitilizes controls for GMMU state
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function enables platform atomic capability mode to rmw atomic
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* through following configuration:
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* NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE
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* NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2
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* NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW
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*/
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void (*init_fs_state)(struct gk20a *g);
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/**
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* @brief Gets master MMU register control
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns register that controls all MMU h/w units.
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*
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* @return u32 register for MMU control.
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*/
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u32 (*mmu_ctrl)(struct gk20a *g);
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/**
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* @brief Gets register control for MMU debug mode
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns register that controls MMU debug mode.
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* In debug mode, MMU translates all faulting engine requests using
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* two dummy pages. One dummy page handles writes, the other dummy
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* page handles reads.
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*
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* @return u32 register for MMU debug mode control.
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*/
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u32 (*mmu_debug_ctrl)(struct gk20a *g);
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/**
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* @brief Gets register address to hold dummy page writes in debug mode.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns register containing the address of the dummy
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* page write in debug mode on a fault.
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*
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* @return u32 register for dummy page write.
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*/
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u32 (*mmu_debug_wr)(struct gk20a *g);
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/**
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* @brief Gets register address to hold dummy page reads in debug mode.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns register containing the address of the dummy
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* page read in debug mode on a fault.
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*
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* @return u32 register for dummy page read.
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*/
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u32 (*mmu_debug_rd)(struct gk20a *g);
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/**
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* @brief Dumps VPR information.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function error logs VPR information that the MMU fetches from
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* memory controller. VPR info has following data:
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* - addr_lo displays the lower address of the VPR
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* - addr_hi displays the upper address of the VPR.
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* - cya_low and cya_hi displays CYA bits the control the
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* trust level of each client.
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*/
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void (*dump_vpr_info)(struct gk20a *g);
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/**
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* @brief Dumps WPR information.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function error logs WPR information that the MMU fetches from
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* memory controller. WPR info has following data:
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* - allow_read displays the read access controls
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* - allow_write displays the write access controls
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* - wpr1_addr_lo displays the lower address of the WPR1
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* - wpr1_addr_hi displays the upper address of the WPR1.
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* - wpr2_addr_lo displays the lower address of the WPR2
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* - wpr2_addr_hi displays the upper address of the WPR2.
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*/
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void (*dump_wpr_info)(struct gk20a *g);
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/**
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* @brief Trigger VPR fetch information.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function triggers VPR fetch and waits until VPR fetch is
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* completed.
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @retval -ETIMEDOUT if CPU polling timeout during VPR fetch.
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*/
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int (*vpr_info_fetch)(struct gk20a *g);
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/**
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* @brief Read WPR info.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param wpr_base [out] WPR base address.
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* @param wpr_size [out] WPR region size.
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*
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* This function reads WPR info and returns WPR base address and
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* WPR size.
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*/
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void (*read_wpr_info)(struct gk20a *g, u64 *wpr_base, u64 *wpr_size);
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/**
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* @brief Invalidate TLB specific to pdb given.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param pdb [in] Pointer to pdb.
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*
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* This function invalidates all va addressed specified by pdb.
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* It includes following steps:
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* - Wait until pri input fifo space available for tlb invalidation.
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* - Setup pdb address space for invalidation.
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* - Trigger invalidate of all va address and wait for completion.
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @retval -ETIMEDOUT if CPU polling timeout during any tlb invalidate
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* operations.
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*/
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int (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb);
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/**
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* @brief Setup mmu fault buffer.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param index [in] Fault buffer index.
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*
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* This function configures mmu fault buffer for h/w and s/w use. When
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* mmu fault occurs h/w will write fault info in the region set-up by
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* s/w for s/w consumption.
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*/
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void (*fault_buf_configure_hw)(struct gk20a *g, u32 index);
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/**
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* @brief Check if mmu fault buffer is enabled or not
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param index [in] Fault buffer index.
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*
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* This function checks and returns whether fault buffer is enabled
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* for specified index.
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*
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* @return true in case of fault buffer enabled, false otherwise.
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*/
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bool (*is_fault_buf_enabled)(struct gk20a *g, u32 index);
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/**
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* @brief Setup mmu fault buffer state.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param index [in] Fault buffer index.
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* @param state [in] NVGPU_MMU_FAULT_BUF_ENABLED or
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* NVGPU_MMU_FAULT_BUF_DISABLED
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*
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* This function set-up mmu fault buffer state.
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* NVGPU_MMU_FAULT_BUF_ENABLED : set the actual size of fault buffer.
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* NVGPU_MMU_FAULT_BUF_DISABLED : Clears fault buffer size.
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*/
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void (*fault_buf_set_state_hw)(struct gk20a *g, u32 index, u32 state);
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struct gops_fb_intr intr;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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void (*set_mmu_page_size)(struct gk20a *g);
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u32 (*read_mmu_fault_buffer_get)(struct gk20a *g, u32 index);
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u32 (*read_mmu_fault_buffer_put)(struct gk20a *g, u32 index);
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u32 (*read_mmu_fault_buffer_size)(struct gk20a *g, u32 index);
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u32 (*read_mmu_fault_info)(struct gk20a *g);
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u32 (*read_mmu_fault_status)(struct gk20a *g);
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void (*write_mmu_fault_buffer_lo_hi)(struct gk20a *g, u32 index,
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u32 addr_lo, u32 addr_hi);
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void (*write_mmu_fault_buffer_get)(struct gk20a *g, u32 index,
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u32 reg_val);
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void (*write_mmu_fault_buffer_size)(struct gk20a *g, u32 index,
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u32 reg_val);
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void (*read_mmu_fault_addr_lo_hi)(struct gk20a *g,
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u32 *addr_lo, u32 *addr_hi);
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void (*read_mmu_fault_inst_lo_hi)(struct gk20a *g,
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u32 *inst_lo, u32 *inst_hi);
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void (*write_mmu_fault_status)(struct gk20a *g, u32 reg_val);
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struct nvgpu_hw_err_inject_info_desc * (*get_hubmmu_err_desc)
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(struct gk20a *g);
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#ifdef CONFIG_NVGPU_COMPRESSION
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void (*cbc_configure)(struct gk20a *g, struct nvgpu_cbc *cbc);
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bool (*set_use_full_comp_tag_line)(struct gk20a *g);
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/*
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* Compression tag line coverage. When mapping a compressible
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* buffer, ctagline is increased when the virtual address
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* crosses over the compression page boundary.
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*/
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u64 (*compression_page_size)(struct gk20a *g);
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/*
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* Minimum page size that can be used for compressible kinds.
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*/
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unsigned int (*compressible_page_size)(struct gk20a *g);
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/*
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* Compressible kind mappings: Mask for the virtual and physical
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* address bits that must match.
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*/
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u64 (*compression_align_mask)(struct gk20a *g);
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#endif
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#ifdef CONFIG_NVGPU_DEBUGGER
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bool (*is_debug_mode_enabled)(struct gk20a *g);
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void (*set_debug_mode)(struct gk20a *g, bool enable);
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void (*set_mmu_debug_mode)(struct gk20a *g, bool enable);
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#endif
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#ifdef CONFIG_NVGPU_REPLAYABLE_FAULT
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void (*handle_replayable_fault)(struct gk20a *g);
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int (*mmu_invalidate_replay)(struct gk20a *g,
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u32 invalidate_replay_val);
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#endif
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#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
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#include "include/nvgpu/nvgpu_next_gops_fb.h"
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#endif
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#ifdef CONFIG_NVGPU_DGPU
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/**
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* @brief Initialize FBPA unit ECC support.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function allocates memory to track the ecc error counts
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* for FBPA unit.
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*
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* @return 0 in case of success, < 0 in case of failure.
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*/
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int (*fbpa_ecc_init)(struct gk20a *g);
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/**
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* @brief Free FBPA unit ECC support.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function deallocates memory allocated for ecc error counts
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* for FBPA unit.
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*/
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void (*fbpa_ecc_free)(struct gk20a *g);
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int (*mem_unlock)(struct gk20a *g);
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int (*init_nvlink)(struct gk20a *g);
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int (*enable_nvlink)(struct gk20a *g);
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size_t (*get_vidmem_size)(struct gk20a *g);
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int (*apply_pdb_cache_war)(struct gk20a *g);
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int (*init_fbpa)(struct gk20a *g);
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void (*handle_fbpa_intr)(struct gk20a *g, u32 fbpa_id);
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#endif
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/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
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};
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#endif /* NVGPU_GOPS_FB_H */
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