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cc7bffd8cd
When generating Doxygen XML, if an inner structure is anonymous, the generated XML will remove the inner structure and merge its members with the parent structure. This is not ideal for tooling, so this patch adds a name to a few anonymous structures. JIRA NVGPU-3510 Change-Id: I42556a6b2a2f9a156d9a74fa894197c845656adc Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2274706 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
109 lines
3.3 KiB
C
109 lines
3.3 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GOPS_SYNC_H
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#define NVGPU_GOPS_SYNC_H
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#include <nvgpu/types.h>
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/**
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* @file
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*
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* Sync HAL interface.
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*/
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struct gk20a;
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struct nvgpu_channel;
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struct nvgpu_mem;
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struct vm_gk20a;
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struct priv_cmd_entry;
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struct nvgpu_semaphore;
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/**
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* Sync HAL operations.
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*
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* @see gpu_ops
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*/
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struct gops_sync {
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#ifdef CONFIG_TEGRA_GK20A_NVHOST
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struct gops_sync_syncpt {
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/**
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* @brief Map syncpoint aperture as read-only.
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*
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* @param vm [in] VM area for channel.
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* @param base_gpu [out] Base GPU VA for mapped
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* syncpoint aperture.
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* @param sync_size [out] Size of syncpoint aperture
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* in bytes.
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*
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* Map syncpoint aperture in GPU virtual memory as read-only:
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* - Acquire syncpoint read-only map lock.
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* - Map syncpoint aperture in sysmem to GPU virtual memory,
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* if not already mapped. Map as read-only.
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* - Release syncpoint read-only map lock.
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @retval -ENOMEM if syncpoint aperture could not be
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* mapped to GPU virtual memory.
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*/
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int (*get_sync_ro_map)(struct vm_gk20a *vm,
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u64 *base_gpuva, u32 *sync_size);
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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int (*alloc_buf)(struct nvgpu_channel *c,
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u32 syncpt_id,
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struct nvgpu_mem *syncpt_buf);
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void (*free_buf)(struct nvgpu_channel *c,
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struct nvgpu_mem *syncpt_buf);
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#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
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void (*add_wait_cmd)(struct gk20a *g,
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struct priv_cmd_entry *cmd, u32 off,
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u32 id, u32 thresh, u64 gpu_va);
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u32 (*get_wait_cmd_size)(void);
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void (*add_incr_cmd)(struct gk20a *g,
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bool wfi_cmd,
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struct priv_cmd_entry *cmd,
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u32 id, u64 gpu_va);
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u32 (*get_incr_cmd_size)(bool wfi_cmd);
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u32 (*get_incr_per_release)(void);
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#endif
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/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
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} syncpt;
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#endif /* CONFIG_TEGRA_GK20A_NVHOST */
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#ifdef CONFIG_NVGPU_KERNEL_MODE_SUBMIT
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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struct gops_sync_sema {
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u32 (*get_wait_cmd_size)(void);
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u32 (*get_incr_cmd_size)(void);
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void (*add_cmd)(struct gk20a *g,
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struct nvgpu_semaphore *s, u64 sema_va,
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struct priv_cmd_entry *cmd,
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u32 off, bool acquire, bool wfi);
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} sema;
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/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
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#endif
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};
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#endif
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