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Add HALs for getting the base vectors for stall and nonstall engine interrupts. The engine interrupt IDs are added to these base vectors to determine the engine stall and nonstall interrupt vectors. Jira NVGPU-9217 Change-Id: Ieaf0e75caac0f7e23684b80466fbf1dc3a57f68d Signed-off-by: Austin Tajiri <atajiri@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2880426 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
53 lines
2.2 KiB
C
53 lines
2.2 KiB
C
/*
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* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_MC_INTR_GA10B_H
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#define NVGPU_MC_INTR_GA10B_H
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#include <nvgpu/types.h>
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struct gk20a;
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void ga10b_intr_host2soc_0_unit_config(struct gk20a *g, u32 unit, bool enable);
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u32 ga10b_intr_host2soc_0(struct gk20a *g);
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void ga10b_intr_host2soc_0_pause(struct gk20a *g);
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void ga10b_intr_host2soc_0_resume(struct gk20a *g);
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u32 ga10b_intr_isr_host2soc_0(struct gk20a *g);
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void ga10b_intr_log_pending_intrs(struct gk20a *g);
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void ga10b_intr_mask_top(struct gk20a *g);
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bool ga10b_intr_is_mmu_fault_pending(struct gk20a *g);
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void ga10b_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable);
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u32 ga10b_intr_stall(struct gk20a *g);
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void ga10b_intr_stall_pause(struct gk20a *g);
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void ga10b_intr_stall_resume(struct gk20a *g);
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void ga10b_intr_isr_stall(struct gk20a *g);
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u32 ga10b_intr_get_eng_nonstall_base_vector(struct gk20a *g);
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u32 ga10b_intr_get_eng_stall_base_vector(struct gk20a *g);
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bool ga10b_intr_is_stall_and_eng_intr_pending(struct gk20a *g, u32 engine_id,
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u32 *eng_intr_pending);
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bool ga10b_mc_intr_get_unit_info(struct gk20a *g, u32 unit);
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#endif /* NVGPU_MC_INTR_GA10B_H */
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