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9a642175d7
MISRA Advisory Rule 10.5 states that the value of an expression should not be cast to an inappropriate essential type. This change removes five violations of this rule that involve casting boolean results to unsigned values: * pass 1/0 (instead of true/false) to nvgpu_atomic operations * fix skip_mask handling in gm20b_gr_init_pd_skip_table_gpc() * fix l3_alloc flags check in nvgpu_gmmu_map_locked() This change also eliminates several MISRA Advisory Rule 4.6 violations. JIRA NVGPU-3798 Change-Id: I707da8a812bfb32eaeb2200463885c0961b197b3 Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2153070 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
69 lines
2.4 KiB
C
69 lines
2.4 KiB
C
/*
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* Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/channel.h>
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#include <nvgpu/log.h>
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#include <nvgpu/atomic.h>
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#include <nvgpu/io.h>
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#include <nvgpu/barrier.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/gk20a.h>
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#include "channel_gm20b.h"
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#include <nvgpu/hw/gm20b/hw_ccsr_gm20b.h>
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#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
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void gm20b_channel_bind(struct nvgpu_channel *c)
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{
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struct gk20a *g = c->g;
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u32 inst_ptr = nvgpu_inst_block_ptr(g, &c->inst_block);
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nvgpu_log_info(g, "bind channel %d inst ptr 0x%08x",
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c->chid, inst_ptr);
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gk20a_writel(g, ccsr_channel_inst_r(c->chid),
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ccsr_channel_inst_ptr_f(inst_ptr) |
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nvgpu_aperture_mask(g, &c->inst_block,
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ccsr_channel_inst_target_sys_mem_ncoh_f(),
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ccsr_channel_inst_target_sys_mem_coh_f(),
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ccsr_channel_inst_target_vid_mem_f()) |
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ccsr_channel_inst_bind_true_f());
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gk20a_writel(g, ccsr_channel_r(c->chid),
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(gk20a_readl(g, ccsr_channel_r(c->chid)) &
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~ccsr_channel_enable_set_f(~U32(0U))) |
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ccsr_channel_enable_set_true_f());
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nvgpu_smp_wmb();
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nvgpu_atomic_set(&c->bound, 1);
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}
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void gm20b_channel_force_ctx_reload(struct nvgpu_channel *ch)
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{
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struct gk20a *g = ch->g;
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u32 reg = gk20a_readl(g, ccsr_channel_r(ch->chid));
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gk20a_writel(g, ccsr_channel_r(ch->chid),
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reg | ccsr_channel_force_ctx_reload_true_f());
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}
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