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47dc0b9ebd
Moved the channel HAL files from common/fifo/ to hal/fifo Jira NVGPU-3248 Change-Id: Ibb85b7c0e71422dbd774a518e4f0bba0b97ef807 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2123399 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
45 lines
1.8 KiB
C
45 lines
1.8 KiB
C
/*
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* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef FIFO_CHANNEL_GV11B_H
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#define FIFO_CHANNEL_GV11B_H
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#include <nvgpu/types.h>
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struct gk20a;
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struct nvgpu_channel;
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struct nvgpu_channel_hw_state;
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struct nvgpu_debug_context;
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struct nvgpu_channel_dump_info;
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void gv11b_channel_unbind(struct nvgpu_channel *ch);
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u32 gv11b_channel_count(struct gk20a *g);
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void gv11b_channel_read_state(struct gk20a *g, struct nvgpu_channel *ch,
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struct nvgpu_channel_hw_state *state);
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void gv11b_channel_reset_faulted(struct gk20a *g, struct nvgpu_channel *ch,
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bool eng, bool pbdma);
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void gv11b_channel_debug_dump(struct gk20a *g,
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struct nvgpu_debug_context *o,
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struct nvgpu_channel_dump_info *info);
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#endif /* FIFO_CHANNEL_GV11B_H */
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