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252ddc4f05
Add macros for whitelisting coverity violations. These macros use pragma directives. The pragma directives and whitelisting macros are only enabled when a coverity scan is being run. The whitelisting macros have been added to a new header called static_analysis.h. The contents of safe_ops.h (CERT C safe ops) have been moved into static_analysis.h because this will be the new header for static analysis related macros/defines/etc. JIRA NVGPU-3820 Change-Id: I9c63f20f670880b420415535738034619314b7c3 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2180600 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
126 lines
3.7 KiB
C
126 lines
3.7 KiB
C
/*
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* Copyright (c) 2015-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/top.h>
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#include <nvgpu/engines.h>
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#include <nvgpu/log.h>
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#include <nvgpu/errno.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/static_analysis.h>
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#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
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#include "engines_gp10b.h"
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int gp10b_engine_init_ce_info(struct nvgpu_fifo *f)
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{
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struct gk20a *g = f->g;
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int ret = 0;
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u32 i;
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enum nvgpu_fifo_engine engine_enum;
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u32 gr_runlist_id;
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u32 pbdma_id = U32_MAX;
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bool found_pbdma_for_runlist = false;
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u32 lce_num_entries = 0;
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gr_runlist_id = nvgpu_engine_get_gr_runlist_id(g);
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nvgpu_log_info(g, "gr_runlist_id: %d", gr_runlist_id);
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if (g->ops.top.get_num_engine_type_entries != NULL) {
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lce_num_entries = g->ops.top.get_num_engine_type_entries(g,
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NVGPU_ENGINE_LCE);
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nvgpu_log_info(g, "lce_num_entries: %d", lce_num_entries);
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}
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for (i = 0; i < lce_num_entries; i++) {
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struct nvgpu_device_info dev_info;
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struct nvgpu_engine_info *info;
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ret = g->ops.top.get_device_info(g, &dev_info,
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NVGPU_ENGINE_LCE, i);
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if (ret != 0) {
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nvgpu_err(g,
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"Failed to parse dev_info for engine%d",
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NVGPU_ENGINE_LCE);
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return -EINVAL;
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}
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found_pbdma_for_runlist =
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g->ops.pbdma.find_for_runlist(g,
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dev_info.runlist_id,
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&pbdma_id);
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if (!found_pbdma_for_runlist) {
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nvgpu_err(g, "busted pbdma map");
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return -EINVAL;
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}
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info = &g->fifo.engine_info[dev_info.engine_id];
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engine_enum = nvgpu_engine_enum_from_type(
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g,
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dev_info.engine_type);
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/* GR and GR_COPY shares same runlist_id */
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if ((engine_enum == NVGPU_ENGINE_ASYNC_CE) &&
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(gr_runlist_id ==
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dev_info.runlist_id)) {
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engine_enum = NVGPU_ENGINE_GRCE;
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}
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info->engine_enum = engine_enum;
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if (g->ops.top.get_ce_inst_id != NULL) {
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dev_info.inst_id = g->ops.top.get_ce_inst_id(g,
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dev_info.engine_type);
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}
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if ((dev_info.fault_id == 0U) &&
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(engine_enum == NVGPU_ENGINE_GRCE)) {
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dev_info.fault_id = 0x1b;
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}
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info->fault_id = dev_info.fault_id;
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info->intr_mask |= BIT32(dev_info.intr_id);
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info->reset_mask |= BIT32(dev_info.reset_id);
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info->runlist_id = dev_info.runlist_id;
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info->pbdma_id = pbdma_id;
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info->inst_id = dev_info.inst_id;
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info->pri_base = dev_info.pri_base;
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/* engine_id starts from 0 to NV_HOST_NUM_ENGINES */
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f->active_engines_list[f->num_engines] =
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dev_info.engine_id;
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f->num_engines = nvgpu_safe_add_u32(f->num_engines, 1U);
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nvgpu_log_info(g, "gr info: engine_id %d runlist_id %d "
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"intr_id %d reset_id %d engine_type %d "
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"engine_enum %d inst_id %d",
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dev_info.engine_id,
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dev_info.runlist_id,
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dev_info.intr_id,
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dev_info.reset_id,
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dev_info.engine_type,
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engine_enum,
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dev_info.inst_id);
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}
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return 0;
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}
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