mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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d8ec4e4e12
Move zcull size initialization to hal.gr.zcull unit. This removes zcull dependency on falcon unit Add new variable zcull_image_size to gr_gk20a.ctx_vars struct Pass the size to nvgpu_gr_zcull_init()/vgpu_gr_init_gr_zcull() as parameter to initialize zcull info Jira NVGPU-3112 Change-Id: I54d966073dad658b4aad3a529f44c0478208b10c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2098507 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
245 lines
8.1 KiB
C
245 lines
8.1 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/io.h>
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#include <nvgpu/gr/config.h>
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#include <nvgpu/gr/subctx.h>
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#include <nvgpu/gr/ctx.h>
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#include <nvgpu/gr/zcull.h>
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#include "common/gr/zcull_priv.h"
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#include "zcull_gm20b.h"
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#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
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int gm20b_gr_init_zcull_hw(struct gk20a *g,
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struct nvgpu_gr_zcull *gr_zcull,
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struct nvgpu_gr_config *gr_config)
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{
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u32 gpc_index, gpc_tpc_count, gpc_zcull_count;
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u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
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bool floorsweep = false;
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u32 rcp_conserv;
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u32 offset;
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gr_zcull->total_aliquots =
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gr_gpc0_zcull_total_ram_size_num_aliquots_f(
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nvgpu_readl(g, gr_gpc0_zcull_total_ram_size_r()));
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for (gpc_index = 0;
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gpc_index < nvgpu_gr_config_get_gpc_count(gr_config);
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gpc_index++) {
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gpc_tpc_count =
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nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc_index);
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gpc_zcull_count =
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nvgpu_gr_config_get_gpc_zcb_count(gr_config, gpc_index);
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if (gpc_zcull_count !=
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nvgpu_gr_config_get_max_zcull_per_gpc_count(gr_config) &&
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gpc_zcull_count < gpc_tpc_count) {
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nvgpu_err(g,
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"zcull_banks (%d) less than tpcs (%d) for gpc (%d)",
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gpc_zcull_count, gpc_tpc_count, gpc_index);
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return -EINVAL;
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}
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if (gpc_zcull_count !=
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nvgpu_gr_config_get_max_zcull_per_gpc_count(gr_config) &&
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gpc_zcull_count != 0U) {
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floorsweep = true;
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}
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}
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/* ceil(1.0f / SM_NUM * gr_gpc0_zcull_sm_num_rcp_conservative__max_v()) */
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rcp_conserv = DIV_ROUND_UP(gr_gpc0_zcull_sm_num_rcp_conservative__max_v(),
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nvgpu_gr_config_get_gpc_tpc_count(gr_config, 0U));
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for (gpc_index = 0;
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gpc_index < nvgpu_gr_config_get_gpc_count(gr_config);
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gpc_index++) {
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offset = gpc_index * gpc_stride;
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if (floorsweep) {
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nvgpu_writel(g, gr_gpc0_zcull_ram_addr_r() + offset,
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gr_gpc0_zcull_ram_addr_row_offset_f(
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nvgpu_gr_config_get_map_row_offset(gr_config)) |
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gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(
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nvgpu_gr_config_get_max_zcull_per_gpc_count(gr_config)));
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} else {
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nvgpu_writel(g, gr_gpc0_zcull_ram_addr_r() + offset,
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gr_gpc0_zcull_ram_addr_row_offset_f(
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nvgpu_gr_config_get_map_row_offset(gr_config)) |
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gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(
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nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc_index)));
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}
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nvgpu_writel(g, gr_gpc0_zcull_fs_r() + offset,
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gr_gpc0_zcull_fs_num_active_banks_f(
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nvgpu_gr_config_get_gpc_zcb_count(gr_config, gpc_index)) |
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gr_gpc0_zcull_fs_num_sms_f(
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nvgpu_gr_config_get_tpc_count(gr_config)));
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nvgpu_writel(g, gr_gpc0_zcull_sm_num_rcp_r() + offset,
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gr_gpc0_zcull_sm_num_rcp_conservative_f(rcp_conserv));
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}
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nvgpu_writel(g, gr_gpcs_ppcs_wwdx_sm_num_rcp_r(),
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gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(rcp_conserv));
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return 0;
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}
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int gm20b_gr_get_zcull_info(struct gk20a *g,
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struct nvgpu_gr_config *gr_config,
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struct nvgpu_gr_zcull *zcull,
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struct nvgpu_gr_zcull_info *zcull_params)
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{
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zcull_params->width_align_pixels = zcull->width_align_pixels;
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zcull_params->height_align_pixels = zcull->height_align_pixels;
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zcull_params->pixel_squares_by_aliquots =
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zcull->pixel_squares_by_aliquots;
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zcull_params->aliquot_total = zcull->total_aliquots;
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zcull_params->region_byte_multiplier =
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nvgpu_gr_config_get_gpc_count(gr_config) *
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gr_zcull_bytes_per_aliquot_per_gpu_v();
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zcull_params->region_header_size =
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nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS) *
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gr_zcull_save_restore_header_bytes_per_gpc_v();
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zcull_params->subregion_header_size =
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nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS) *
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gr_zcull_save_restore_subregion_header_bytes_per_gpc_v();
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zcull_params->subregion_width_align_pixels =
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nvgpu_gr_config_get_tpc_count(gr_config) *
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gr_gpc0_zcull_zcsize_width_subregion__multiple_v();
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zcull_params->subregion_height_align_pixels =
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gr_gpc0_zcull_zcsize_height_subregion__multiple_v();
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zcull_params->subregion_count = gr_zcull_subregion_qty_v();
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return 0;
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}
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void gm20b_gr_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries,
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u32 *zcull_map_tiles)
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{
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u32 val;
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nvgpu_log_fn(g, " ");
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if (zcull_num_entries >= 8U) {
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nvgpu_log_fn(g, "map0");
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val =
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gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(
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zcull_map_tiles[0]) |
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gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(
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zcull_map_tiles[1]) |
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gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(
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zcull_map_tiles[2]) |
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gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(
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zcull_map_tiles[3]) |
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gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(
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zcull_map_tiles[4]) |
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gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(
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zcull_map_tiles[5]) |
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gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(
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zcull_map_tiles[6]) |
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gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(
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zcull_map_tiles[7]);
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gk20a_writel(g, gr_gpcs_zcull_sm_in_gpc_number_map0_r(), val);
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}
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if (zcull_num_entries >= 16U) {
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nvgpu_log_fn(g, "map1");
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val =
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gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(
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zcull_map_tiles[8]) |
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gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(
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zcull_map_tiles[9]) |
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gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(
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zcull_map_tiles[10]) |
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gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(
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zcull_map_tiles[11]) |
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gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(
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zcull_map_tiles[12]) |
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gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(
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zcull_map_tiles[13]) |
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gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(
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zcull_map_tiles[14]) |
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gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(
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zcull_map_tiles[15]);
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gk20a_writel(g, gr_gpcs_zcull_sm_in_gpc_number_map1_r(), val);
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}
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if (zcull_num_entries >= 24U) {
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nvgpu_log_fn(g, "map2");
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val =
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gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(
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zcull_map_tiles[16]) |
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gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(
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zcull_map_tiles[17]) |
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gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(
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zcull_map_tiles[18]) |
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gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(
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zcull_map_tiles[19]) |
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gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(
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zcull_map_tiles[20]) |
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gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(
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zcull_map_tiles[21]) |
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gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(
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zcull_map_tiles[22]) |
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gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(
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zcull_map_tiles[23]);
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gk20a_writel(g, gr_gpcs_zcull_sm_in_gpc_number_map2_r(), val);
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}
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if (zcull_num_entries >= 32U) {
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nvgpu_log_fn(g, "map3");
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val =
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gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(
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zcull_map_tiles[24]) |
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gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(
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zcull_map_tiles[25]) |
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gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(
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zcull_map_tiles[26]) |
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gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(
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zcull_map_tiles[27]) |
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gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(
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zcull_map_tiles[28]) |
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gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(
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zcull_map_tiles[29]) |
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gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(
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zcull_map_tiles[30]) |
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gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(
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zcull_map_tiles[31]);
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gk20a_writel(g, gr_gpcs_zcull_sm_in_gpc_number_map3_r(), val);
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}
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}
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