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06fd513e1e
nvgpu.common.unit was just an enum used for passing to nvgpu.common.mc APIs. So, move the enum into mc.h, and replace the include of unit.h with mc.h where appropriate. And update the yaml arch. JIRA NVGPU-4144 Change-Id: I210ea4d3b49cd494e43add1b52f3fbcdb020a1e3 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2216106 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
115 lines
3.6 KiB
C
115 lines
3.6 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/io.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/mc.h>
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#include "perf_gv11b.h"
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#include <nvgpu/hw/gv11b/hw_perf_gv11b.h>
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bool gv11b_perf_get_membuf_overflow_status(struct gk20a *g)
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{
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const u32 st = perf_pmasys_control_membuf_status_overflowed_f();
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return st == (nvgpu_readl(g, perf_pmasys_control_r()) & st);
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}
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u32 gv11b_perf_get_membuf_pending_bytes(struct gk20a *g)
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{
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return nvgpu_readl(g, perf_pmasys_mem_bytes_r());
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}
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void gv11b_perf_set_membuf_handled_bytes(struct gk20a *g,
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u32 entries, u32 entry_size)
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{
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if (entries > 0U) {
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nvgpu_writel(g, perf_pmasys_mem_bump_r(), entries * entry_size);
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}
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}
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void gv11b_perf_membuf_reset_streaming(struct gk20a *g)
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{
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u32 engine_status;
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u32 num_unread_bytes;
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g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON));
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engine_status = nvgpu_readl(g, perf_pmasys_enginestatus_r());
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WARN_ON(0U ==
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(engine_status & perf_pmasys_enginestatus_rbufempty_empty_f()));
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nvgpu_writel(g, perf_pmasys_control_r(),
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perf_pmasys_control_membuf_clear_status_doit_f());
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num_unread_bytes = nvgpu_readl(g, perf_pmasys_mem_bytes_r());
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if (num_unread_bytes != 0U) {
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nvgpu_writel(g, perf_pmasys_mem_bump_r(), num_unread_bytes);
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}
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}
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void gv11b_perf_enable_membuf(struct gk20a *g, u32 size,
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u64 buf_addr, struct nvgpu_mem *inst_block)
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{
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u32 addr_lo;
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u32 addr_hi;
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u32 inst_block_ptr;
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addr_lo = u64_lo32(buf_addr);
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addr_hi = u64_hi32(buf_addr);
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nvgpu_writel(g, perf_pmasys_outbase_r(), addr_lo);
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nvgpu_writel(g, perf_pmasys_outbaseupper_r(),
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perf_pmasys_outbaseupper_ptr_f(addr_hi));
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nvgpu_writel(g, perf_pmasys_outsize_r(), size);
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inst_block_ptr = nvgpu_inst_block_ptr(g, inst_block);
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nvgpu_writel(g, perf_pmasys_mem_block_r(),
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perf_pmasys_mem_block_base_f(inst_block_ptr) |
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perf_pmasys_mem_block_valid_true_f() |
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nvgpu_aperture_mask(g, inst_block,
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perf_pmasys_mem_block_target_sys_ncoh_f(),
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perf_pmasys_mem_block_target_sys_coh_f(),
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perf_pmasys_mem_block_target_lfb_f()));
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}
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void gv11b_perf_disable_membuf(struct gk20a *g)
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{
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nvgpu_writel(g, perf_pmasys_outbase_r(), 0);
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nvgpu_writel(g, perf_pmasys_outbaseupper_r(),
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perf_pmasys_outbaseupper_ptr_f(0));
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nvgpu_writel(g, perf_pmasys_outsize_r(), 0);
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nvgpu_writel(g, perf_pmasys_mem_block_r(),
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perf_pmasys_mem_block_base_f(0) |
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perf_pmasys_mem_block_valid_false_f() |
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perf_pmasys_mem_block_target_f(0));
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}
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u32 gv11b_perf_get_pmm_per_chiplet_offset(void)
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{
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return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1U);
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}
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