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IRQs can get triggered during nvgpu power-on due to MMU fault, invalid PRIV ring or bus access etc. Handlers for those IRQs can't access the full state related to the IRQ unless nvgpu is fully powered on. In order to let the IRQ handlers know about the nvgpu power-on state gk20a.power_on_state variable has to be protected through spinlock to avoid the deadlock due to usage of earlier power_lock mutex. Further the IRQs need to be disabled on local CPU while updating the power state variable hence use spin_lock_irqsave and spin_unlock_- irqrestore APIs for protecting the access. JIRA NVGPU-1592 Change-Id: If5d1b5e2617ad90a68faa56ff47f62bb3f0b232b Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2203860 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
217 lines
4.7 KiB
C
217 lines
4.7 KiB
C
/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <unistd.h>
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#include <stdlib.h>
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#include <pthread.h>
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#include <nvgpu/bug.h>
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#include <nvgpu/types.h>
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#include <nvgpu/atomic.h>
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#include <nvgpu/nvgpu_common.h>
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#include <nvgpu/nvgpu_init.h>
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#include <nvgpu/os_sched.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/enabled.h>
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#include <nvgpu/posix/probe.h>
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#include "os_posix.h"
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#ifdef NVGPU_UNITTEST_FAULT_INJECTION_ENABLEMENT
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#include <nvgpu/posix/posix-fault-injection.h>
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#endif
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#ifdef NVGPU_UNITTEST_FAULT_INJECTION_ENABLEMENT
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_Thread_local struct nvgpu_posix_fault_inj nvgpu_fi;
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struct nvgpu_posix_fault_inj *nvgpu_nvgpu_get_fault_injection(void)
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{
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return &nvgpu_fi;
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}
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#endif
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/*
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* Somewhat meaningless in userspace...
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*/
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void nvgpu_kernel_restart(void *cmd)
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{
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BUG();
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}
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void nvgpu_start_gpu_idle(struct gk20a *g)
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{
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nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
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}
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int nvgpu_enable_irqs(struct gk20a *g)
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{
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return 0;
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}
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void nvgpu_disable_irqs(struct gk20a *g)
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{
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}
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void nvgpu_set_power_state(struct gk20a *g, u32 state)
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{
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nvgpu_spinlock_acquire(&g->power_spinlock);
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g->power_on_state = state;
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nvgpu_spinlock_release(&g->power_spinlock);
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}
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const char *nvgpu_get_power_state(struct gk20a *g)
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{
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const char *str = NULL;
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u32 state;
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nvgpu_spinlock_acquire(&g->power_spinlock);
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state = g->power_on_state;
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nvgpu_spinlock_release(&g->power_spinlock);
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switch (state) {
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case NVGPU_STATE_POWERED_OFF:
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str = "off";
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break;
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case NVGPU_STATE_POWERING_ON:
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str = "powering on";
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break;
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case NVGPU_STATE_POWERED_ON:
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str = "on";
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break;
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default:
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nvgpu_err(g, "Invalid nvgpu power state.");
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break;
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}
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return str;
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}
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bool nvgpu_is_powered_on(struct gk20a *g)
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{
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u32 power_on;
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nvgpu_spinlock_acquire(&g->power_spinlock);
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power_on = g->power_on_state;
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nvgpu_spinlock_release(&g->power_spinlock);
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return power_on == NVGPU_STATE_POWERED_ON;
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}
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bool nvgpu_is_powered_off(struct gk20a *g)
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{
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u32 power_on;
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nvgpu_spinlock_acquire(&g->power_spinlock);
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power_on = g->power_on_state;
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nvgpu_spinlock_release(&g->power_spinlock);
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return power_on == NVGPU_STATE_POWERED_OFF;
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}
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/*
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* We have no runtime PM stuff in userspace so these are really just noops.
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*/
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void gk20a_busy_noresume(struct gk20a *g)
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{
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}
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void gk20a_idle_nosuspend(struct gk20a *g)
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{
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}
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int gk20a_busy(struct gk20a *g)
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{
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#ifdef NVGPU_UNITTEST_FAULT_INJECTION_ENABLEMENT
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if (nvgpu_posix_fault_injection_handle_call(&nvgpu_fi)) {
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return -ENODEV;
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}
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#endif
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nvgpu_atomic_inc(&g->usage_count);
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return 0;
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}
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void gk20a_idle(struct gk20a *g)
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{
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nvgpu_atomic_dec(&g->usage_count);
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}
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/*
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* This function aims to initialize enough stuff to make unit testing worth
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* while. There are several interfaces and APIs that rely on the struct gk20a's
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* state in order to function: logging, for example, but there are many other
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* things, too.
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*
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* Initialize as much of that as possible here. This is meant to be equivalent
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* to the kernel space driver's probe function.
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*/
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struct gk20a *nvgpu_posix_probe(void)
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{
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struct gk20a *g;
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struct nvgpu_os_posix *p;
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#ifdef NVGPU_UNITTEST_FAULT_INJECTION_ENABLEMENT
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if (nvgpu_posix_fault_injection_handle_call(&nvgpu_fi)) {
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return NULL;
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}
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#endif
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p = malloc(sizeof(*p));
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if (p == NULL) {
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return NULL;
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}
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(void) memset(p, 0, sizeof(*p));
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g = &p->g;
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g->log_mask = 0;
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g->mm.g = g;
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if (nvgpu_kmem_init(g) != 0) {
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goto fail_kmem;
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}
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if (nvgpu_init_enabled_flags(g) != 0) {
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goto fail_enabled_flags;
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}
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return g;
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fail_enabled_flags:
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nvgpu_kmem_fini(g, 0);
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fail_kmem:
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free(p);
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return NULL;
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}
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void nvgpu_posix_cleanup(struct gk20a *g)
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{
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struct nvgpu_os_posix *p = nvgpu_os_posix_from_gk20a(g);
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nvgpu_kmem_fini(g, 0);
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nvgpu_free_enabled_flags(g);
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free(p);
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}
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