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This adds the SWUTS documentation for nvgpu-runlist unit tests: - test_tsg_format_gen - test_flat - test_flat_oversize_tiny - test_flat_oversize_single - test_flat_oversize_onehalf - test_flat_oversize_two - test_flat_oversize_end - test_interleaving_gen_all_run - test_interleaving_l0 - test_interleaving_l1 - test_interleaving_l2 - test_interleaving_l0_l1 - test_interleaving_l1_l2 - test_interleaving_l0_l2 Jira NVGPU-3943 Change-Id: I569a936346a4726f506d338b54157212529c3be8 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2202477 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
322 lines
10 KiB
C
322 lines
10 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef UNIT_NVGPU_RUNLIST_H
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#define UNIT_NVGPU_RUNLIST_H
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#include <nvgpu/types.h>
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struct unit_module;
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struct gk20a;
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/** @addtogroup SWUTS-fifo-runlist
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* @{
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*
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* Software Unit Test Specification for fifo/runlist */
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/**
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* Test specification for: test_tsg_format_gen
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*
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* Description: Test format of TSG runlist entry
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*
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* Test Type: Feature based
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*
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* Input: None
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*
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* Steps:
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* - Check that inserting a single TSG of any level with a number of channels
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* works as expected:
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* - priority 0, one channel.
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* - priority 1, two channels.
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* - priority 2, five channels.
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* - priority 0, one channel, nondefault timeslice timeout.
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* - priority 0, three channels with two inactives in the middle.
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* - Each entry in #tsg_fmt_tests describes one subtest above:
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* - number of channels to be allocated.
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* - runlist interleavel level.
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* - runlist timeslice.
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* - expected RL entry (header+channels).
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*
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* After allocating channels and binding them to TSG, the TSG is added to
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* runlist by calling nvgpu_runlist_construct_locked.
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* Then entries of the runlist are checked against expected values (as
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* specified by #tsg_fmt_tests).
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_tsg_format_gen(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_flat
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*
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* Description: Build runlist without interleaving (aka "flat")
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*
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* Test Type: Feature based
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*
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* Input: None
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*
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* Steps:
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* - Allocate TSGs, each bound to multiple channels.
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* - Add TSGs to runlist, using pseudo-random priorites for TSGs.
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* - Flat runlist is used: interleave is set to false when calling
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* nvgpu_runlist_construct_locked.
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* - Check that resulting runlist is ordered according to priorities
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* (higher priorities first).
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_flat(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_flat_oversize_tiny
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*
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* Description: Only one TSG header can fit the runlist
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* (not even its channels)
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*
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* Test Type: Feature based
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*
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* Input: None
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*
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* Steps:
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* - Same as #test_flat, except that runlist size
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* is set to 1 entry, and that failure is expected when
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* calling nvgpu_runlist_construct_locked.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_flat_oversize_tiny(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_flat_oversize_single
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*
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* Description: Only one TSG header with its channels fits the runlist
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*
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* Test Type: Feature based
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*
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* Input: None
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*
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* Steps:
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* - Same as #test_flat, except that runlist size
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* is set to 2 entries, and that failure is expected when
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* calling nvgpu_runlist_construct_locked.
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* - Check that whatever was inserted in the runlist matches expected TSGs.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_flat_oversize_single(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_flat_oversize_onehalf
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*
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* Description: Second TSG's channels are chopped off.
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*
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* Test Type: Feature based
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*
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* Input: None
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*
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* Steps:
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* - Same as #test_flat, except that runlist size
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* is set to 3 entries, and that failure is expected when
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* calling nvgpu_runlist_construct_locked.
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* - Check that whatever was inserted in the runlist matches expected TSGs.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_flat_oversize_onehalf(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_flat_oversize_two
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*
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* Description: Two full TSG entries fit exactly
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*
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* Test Type: Feature based
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*
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* Input: None
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*
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* Steps:
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* - Same as #test_flat, except that runlist size
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* is set to 4 entries, and that failure is expected when
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* calling nvgpu_runlist_construct_locked.
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* - Check that whatever was inserted in the runlist matches expected TSGs.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_flat_oversize_two(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_flat_oversize_end
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*
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* Description: All but the last channel entry fit.
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*
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* Test Type: Feature based
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*
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* Input: None
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*
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* Steps:
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* - Same as #test_flat, except that runlist size
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* is set to (n x TSG - 1) entries, and that failure is expected when
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* calling nvgpu_runlist_construct_locked.
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* - Check that whatever was inserted in the runlist matches expected TSGs.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_flat_oversize_end(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_interleaving_gen_all_run
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*
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* Description: Build runlist with interleaving, all levels
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*
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* Test Type: Feature based
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*
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* Input: None
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*
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* Steps:
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* - Create TSGs and channels, such that the first two TSGs, IDs 0 and 1
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* (with just one channel each) are at interleave level "low" ("l0"), the
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* next IDs 2 and 3 are at level "med" ("l1"), and the last IDs 4 and 5
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* are at level "hi" ("l2"). Runlist construction doesn't care, so we use
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* an easy to understand order.
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* - When debugging this test and/or the runlist code, the logs of any
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* interleave test should follow the order in the "expected" array. We
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* start at the highest level, so the first IDs added should be h1 and
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* h2, i.e., 4 and 5, etc.
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* - TSGs are added to runlists using nvgpu_runlist_construct_locked, with
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* interleave enabled.
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* - Expected order of TSGs is stored in an array, and actual runlist is
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* compared with expected order.
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* - If runlist is too small to accomodate all TSGs/channels, an error
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* is expected for nvgpu_runlist_construct_locked, and actual truncated
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* runlist is compared with first elements of expected array.
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* - This test runs for levels: l0, l1, l2.
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_interleaving_gen_all_run(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_interleaving_l0
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*
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* Description: Build runlist with interleaving, l0 level only
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*
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* Test Type: Feature based
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*
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* Input: None
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*
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* Steps:
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* - Same as #test_interleaving_gen_all_run but with only two TSGs
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* which are at interleave level "low" (l0)
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_interleaving_l0(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_interleaving_l1
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*
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* Description: Build runlist with interleaving, l1 level only
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*
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* Test Type: Feature based
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*
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* Input: None
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*
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* Steps:
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* - Same as #test_interleaving_gen_all_run but with only two TSGs
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* which are at interleave level "med" (l1).
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_interleaving_l1(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_interleaving_l2
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*
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* Description: Build runlist with interleaving, l2 level only
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*
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* Test Type: Feature based
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*
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* Input: None
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*
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* Steps:
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* - Same as #test_interleaving_gen_all_run but with only two TSGs
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* which are at interleave level "high" (l2)
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_interleaving_l2(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_interleaving_l0_l1
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*
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* Description: Build runlist with interleaving, l0 and l1 levels
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*
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* Test Type: Feature based
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*
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* Input: None
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*
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* Steps:
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* - Same as #test_interleaving_gen_all_run but with low and medium
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* interleave level TSGs (l0 and l1)
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_interleaving_l0_l1(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_interleaving_l1_l2
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*
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* Description: Build runlist with interleaving, l1 and l2 levels
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*
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* Test Type: Feature based
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*
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* Input: None
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*
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* Steps:
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* - Same as #test_interleaving_gen_all_run but with medium and high
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* interleave level TSGs (l1 and l2)
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_interleaving_l1_l2(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* Test specification for: test_interleaving_l0_l2
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*
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* Description: Build runlist with interleaving, l0 and l2 levels
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*
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* Test Type: Feature based
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*
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* Input: None
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*
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* Steps:
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* - Same as #test_interleaving_gen_all_run but with low and high
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* interleave level TSGs (l0 and l2)
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
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*/
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int test_interleaving_l0_l2(struct unit_module *m, struct gk20a *g, void *args);
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/**
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* @}
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*/
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#endif /* UNIT_NVGPU_RUNLIST_H */
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