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361eca66b5
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I604d85367cd4b99c39df2b9fa2d7a7219ef941d5 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807153 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
91 lines
2.7 KiB
C
91 lines
2.7 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "gk20a/gk20a.h"
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#include "boardobj.h"
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#include "boardobjgrp_e255.h"
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#include "ctrl/ctrlboardobj.h"
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#include "boardobjgrp.h"
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#include "boardobjgrpmask.h"
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u32 boardobjgrpconstruct_e255(struct gk20a *g,
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struct boardobjgrp_e255 *pboardobjgrp_e255)
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{
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u32 status = 0;
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u8 objslots;
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nvgpu_log_info(g, " ");
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objslots = 255;
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status = boardobjgrpmask_e255_init(&pboardobjgrp_e255->mask, NULL);
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if (status) {
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goto boardobjgrpconstruct_e255_exit;
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}
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pboardobjgrp_e255->super.type = CTRL_BOARDOBJGRP_TYPE_E255;
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pboardobjgrp_e255->super.ppobjects = pboardobjgrp_e255->objects;
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pboardobjgrp_e255->super.objslots = objslots;
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pboardobjgrp_e255->super.mask = &(pboardobjgrp_e255->mask.super);
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status = boardobjgrp_construct_super(g, &pboardobjgrp_e255->super);
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if (status) {
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goto boardobjgrpconstruct_e255_exit;
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}
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pboardobjgrp_e255->super.pmuhdrdatainit =
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boardobjgrp_pmuhdrdatainit_e255;
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boardobjgrpconstruct_e255_exit:
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return status;
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}
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u32 boardobjgrp_pmuhdrdatainit_e255(struct gk20a *g,
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struct boardobjgrp *pboardobjgrp,
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struct nv_pmu_boardobjgrp_super *pboardobjgrppmu,
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struct boardobjgrpmask *mask)
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{
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struct nv_pmu_boardobjgrp_e255 *pgrpe255 =
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(struct nv_pmu_boardobjgrp_e255 *)pboardobjgrppmu;
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u32 status;
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nvgpu_log_info(g, " ");
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if (pboardobjgrp == NULL) {
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return -EINVAL;
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}
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if (pboardobjgrppmu == NULL) {
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return -EINVAL;
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}
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status = boardobjgrpmask_export(mask,
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mask->bitcount,
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&pgrpe255->obj_mask.super);
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if (status) {
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nvgpu_err(g, "e255 init:failed export grpmask");
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return status;
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}
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return boardobjgrp_pmuhdrdatainit_super(g,
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pboardobjgrp, pboardobjgrppmu, mask);
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}
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