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MISRA Rule 11.6 prohibits the casting of an integer value to a void *. The nvgpu allocator used for the fence pool stores the base address of the associated memory as a u64 and returns it via nvgpu_alloc_base(). In gk20a_free_fence_pool() this u64 value was cast to a void * before being passed to nvgpu_vfree() (leading to the violation). This change modifies gk20a_free_fence_pool() to cast the base address back to the original struct gk20a_fence * to eliminate the violation. JIRA NVGPU-895: MISRA Rule 11.6 violations Change-Id: If89cf2c1bc8ea4b0b59da4cf8b1c167738f6badc Signed-off-by: Scott Long <scottl@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774530 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
305 lines
7.4 KiB
C
305 lines
7.4 KiB
C
/*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "fence_gk20a.h"
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#include <nvgpu/semaphore.h>
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#include <nvgpu/kmem.h>
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#include <nvgpu/soc.h>
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#include <nvgpu/nvhost.h>
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#include <nvgpu/barrier.h>
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#include <nvgpu/os_fence.h>
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#include "gk20a.h"
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#include "channel_gk20a.h"
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struct gk20a_fence_ops {
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int (*wait)(struct gk20a_fence *, long timeout);
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bool (*is_expired)(struct gk20a_fence *);
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void *(*free)(struct nvgpu_ref *);
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};
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static void gk20a_fence_free(struct nvgpu_ref *ref)
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{
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struct gk20a_fence *f =
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container_of(ref, struct gk20a_fence, ref);
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struct gk20a *g = f->g;
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if (nvgpu_os_fence_is_initialized(&f->os_fence))
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f->os_fence.ops->drop_ref(&f->os_fence);
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if (f->semaphore)
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nvgpu_semaphore_put(f->semaphore);
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if (f->allocator) {
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if (nvgpu_alloc_initialized(f->allocator))
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nvgpu_free(f->allocator, (u64)(uintptr_t)f);
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} else
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nvgpu_kfree(g, f);
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}
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void gk20a_fence_put(struct gk20a_fence *f)
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{
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if (f)
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nvgpu_ref_put(&f->ref, gk20a_fence_free);
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}
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struct gk20a_fence *gk20a_fence_get(struct gk20a_fence *f)
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{
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if (f)
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nvgpu_ref_get(&f->ref);
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return f;
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}
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inline bool gk20a_fence_is_valid(struct gk20a_fence *f)
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{
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bool valid = f->valid;
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nvgpu_smp_rmb();
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return valid;
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}
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int gk20a_fence_install_fd(struct gk20a_fence *f, int fd)
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{
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if (!f || !gk20a_fence_is_valid(f) ||
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!nvgpu_os_fence_is_initialized(&f->os_fence))
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return -EINVAL;
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f->os_fence.ops->install_fence(&f->os_fence, fd);
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return 0;
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}
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int gk20a_fence_wait(struct gk20a *g, struct gk20a_fence *f,
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unsigned long timeout)
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{
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if (f && gk20a_fence_is_valid(f)) {
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if (!nvgpu_platform_is_silicon(g))
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timeout = MAX_SCHEDULE_TIMEOUT;
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return f->ops->wait(f, timeout);
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}
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return 0;
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}
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bool gk20a_fence_is_expired(struct gk20a_fence *f)
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{
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if (f && gk20a_fence_is_valid(f) && f->ops)
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return f->ops->is_expired(f);
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else
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return true;
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}
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int gk20a_alloc_fence_pool(struct channel_gk20a *c, unsigned int count)
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{
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int err;
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size_t size;
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struct gk20a_fence *fence_pool = NULL;
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size = sizeof(struct gk20a_fence);
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if (count <= UINT_MAX / size) {
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size = count * size;
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fence_pool = nvgpu_vzalloc(c->g, size);
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}
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if (!fence_pool)
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return -ENOMEM;
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err = nvgpu_lockless_allocator_init(c->g, &c->fence_allocator,
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"fence_pool", (size_t)fence_pool, size,
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sizeof(struct gk20a_fence), 0);
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if (err)
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goto fail;
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return 0;
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fail:
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nvgpu_vfree(c->g, fence_pool);
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return err;
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}
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void gk20a_free_fence_pool(struct channel_gk20a *c)
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{
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if (nvgpu_alloc_initialized(&c->fence_allocator)) {
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struct gk20a_fence *fence_pool;
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fence_pool = (struct gk20a_fence *)(uintptr_t)
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nvgpu_alloc_base(&c->fence_allocator);
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nvgpu_alloc_destroy(&c->fence_allocator);
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nvgpu_vfree(c->g, fence_pool);
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}
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}
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struct gk20a_fence *gk20a_alloc_fence(struct channel_gk20a *c)
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{
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struct gk20a_fence *fence = NULL;
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if (channel_gk20a_is_prealloc_enabled(c)) {
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if (nvgpu_alloc_initialized(&c->fence_allocator)) {
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fence = (struct gk20a_fence *)(uintptr_t)
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nvgpu_alloc(&c->fence_allocator,
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sizeof(struct gk20a_fence));
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/* clear the node and reset the allocator pointer */
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if (fence) {
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memset(fence, 0, sizeof(*fence));
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fence->allocator = &c->fence_allocator;
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}
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}
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} else
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fence = nvgpu_kzalloc(c->g, sizeof(struct gk20a_fence));
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if (fence) {
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nvgpu_ref_init(&fence->ref);
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fence->g = c->g;
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}
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return fence;
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}
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void gk20a_init_fence(struct gk20a_fence *f,
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const struct gk20a_fence_ops *ops,
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struct nvgpu_os_fence os_fence)
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{
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if (!f)
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return;
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f->ops = ops;
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f->syncpt_id = -1;
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f->semaphore = NULL;
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f->os_fence = os_fence;
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}
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/* Fences that are backed by GPU semaphores: */
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static int nvgpu_semaphore_fence_wait(struct gk20a_fence *f, long timeout)
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{
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if (!nvgpu_semaphore_is_acquired(f->semaphore))
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return 0;
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return NVGPU_COND_WAIT_INTERRUPTIBLE(
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f->semaphore_wq,
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!nvgpu_semaphore_is_acquired(f->semaphore),
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timeout);
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}
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static bool nvgpu_semaphore_fence_is_expired(struct gk20a_fence *f)
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{
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return !nvgpu_semaphore_is_acquired(f->semaphore);
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}
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static const struct gk20a_fence_ops nvgpu_semaphore_fence_ops = {
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.wait = &nvgpu_semaphore_fence_wait,
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.is_expired = &nvgpu_semaphore_fence_is_expired,
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};
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/* This function takes ownership of the semaphore as well as the os_fence */
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int gk20a_fence_from_semaphore(
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struct gk20a_fence *fence_out,
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struct nvgpu_semaphore *semaphore,
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struct nvgpu_cond *semaphore_wq,
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struct nvgpu_os_fence os_fence)
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{
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struct gk20a_fence *f = fence_out;
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gk20a_init_fence(f, &nvgpu_semaphore_fence_ops, os_fence);
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if (!f)
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return -EINVAL;
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f->semaphore = semaphore;
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f->semaphore_wq = semaphore_wq;
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/* commit previous writes before setting the valid flag */
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nvgpu_smp_wmb();
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f->valid = true;
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return 0;
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}
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#ifdef CONFIG_TEGRA_GK20A_NVHOST
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/* Fences that are backed by host1x syncpoints: */
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static int gk20a_syncpt_fence_wait(struct gk20a_fence *f, long timeout)
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{
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return nvgpu_nvhost_syncpt_wait_timeout_ext(
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f->nvhost_dev, f->syncpt_id, f->syncpt_value,
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(u32)timeout, NULL, NULL);
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}
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static bool gk20a_syncpt_fence_is_expired(struct gk20a_fence *f)
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{
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/*
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* In cases we don't register a notifier, we can't expect the
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* syncpt value to be updated. For this case, we force a read
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* of the value from HW, and then check for expiration.
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*/
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if (!nvgpu_nvhost_syncpt_is_expired_ext(f->nvhost_dev, f->syncpt_id,
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f->syncpt_value)) {
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u32 val;
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if (!nvgpu_nvhost_syncpt_read_ext_check(f->nvhost_dev,
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f->syncpt_id, &val)) {
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return nvgpu_nvhost_syncpt_is_expired_ext(
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f->nvhost_dev,
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f->syncpt_id, f->syncpt_value);
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}
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}
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return true;
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}
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static const struct gk20a_fence_ops gk20a_syncpt_fence_ops = {
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.wait = &gk20a_syncpt_fence_wait,
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.is_expired = &gk20a_syncpt_fence_is_expired,
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};
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/* This function takes the ownership of the os_fence */
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int gk20a_fence_from_syncpt(
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struct gk20a_fence *fence_out,
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struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id, u32 value, struct nvgpu_os_fence os_fence)
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{
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struct gk20a_fence *f = fence_out;
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gk20a_init_fence(f, &gk20a_syncpt_fence_ops, os_fence);
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if (!f)
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return -EINVAL;
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f->nvhost_dev = nvhost_dev;
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f->syncpt_id = id;
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f->syncpt_value = value;
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/* commit previous writes before setting the valid flag */
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nvgpu_smp_wmb();
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f->valid = true;
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return 0;
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}
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#else
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int gk20a_fence_from_syncpt(
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struct gk20a_fence *fence_out,
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struct nvgpu_nvhost_dev *nvhost_dev,
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u32 id, u32 value, struct nvgpu_os_fence os_fence)
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{
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return -EINVAL;
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}
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#endif
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