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4032e8915a
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I1651ae8ee680bdeb48606569c4e8c2fc7cb87f20 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805077 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
90 lines
2.3 KiB
C
90 lines
2.3 KiB
C
/*
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* GM20B MMU
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*
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* Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/sizes.h>
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#include "gk20a/gk20a.h"
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#include "mm_gm20b.h"
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#include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h>
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#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
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void gm20b_mm_set_big_page_size(struct gk20a *g,
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struct nvgpu_mem *mem, int size)
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{
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u32 val;
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nvgpu_log_fn(g, " ");
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nvgpu_log_info(g, "big page size %d\n", size);
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val = nvgpu_mem_rd32(g, mem, ram_in_big_page_size_w());
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val &= ~ram_in_big_page_size_m();
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if (size == SZ_64K) {
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val |= ram_in_big_page_size_64kb_f();
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} else {
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val |= ram_in_big_page_size_128kb_f();
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}
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nvgpu_mem_wr32(g, mem, ram_in_big_page_size_w(), val);
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nvgpu_log_fn(g, "done");
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}
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u32 gm20b_mm_get_big_page_sizes(void)
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{
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return SZ_64K | SZ_128K;
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}
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u32 gm20b_mm_get_default_big_page_size(void)
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{
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return SZ_64K;
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}
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bool gm20b_mm_support_sparse(struct gk20a *g)
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{
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return true;
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}
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bool gm20b_mm_is_bar1_supported(struct gk20a *g)
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{
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return true;
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}
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u64 gm20b_gpu_phys_addr(struct gk20a *g,
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struct nvgpu_gmmu_attrs *attrs, u64 phys)
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{
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return phys;
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}
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u32 gm20b_get_kind_invalid(void)
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{
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return gmmu_pte_kind_invalid_v();
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}
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u32 gm20b_get_kind_pitch(void)
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{
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return gmmu_pte_kind_pitch_v();
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}
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