mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-23 01:50:07 +03:00
e3710e5431
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I8493274995ed8de526902dd0ca0808b2972e28aa Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1796806 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
48 lines
1.7 KiB
C
48 lines
1.7 KiB
C
/*
|
|
* GP106 memory management
|
|
*
|
|
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#include <nvgpu/sizes.h>
|
|
#include <nvgpu/io.h>
|
|
|
|
#include "gk20a/gk20a.h"
|
|
#include "gp10b/mm_gp10b.h"
|
|
#include "gp106/mm_gp106.h"
|
|
|
|
#include <nvgpu/hw/gp106/hw_fb_gp106.h>
|
|
|
|
size_t gp106_mm_get_vidmem_size(struct gk20a *g)
|
|
{
|
|
u32 range = gk20a_readl(g, fb_mmu_local_memory_range_r());
|
|
u32 mag = fb_mmu_local_memory_range_lower_mag_v(range);
|
|
u32 scale = fb_mmu_local_memory_range_lower_scale_v(range);
|
|
u32 ecc = fb_mmu_local_memory_range_ecc_mode_v(range);
|
|
size_t bytes = ((size_t)mag << scale) * SZ_1M;
|
|
|
|
if (ecc) {
|
|
bytes = bytes / 16 * 15;
|
|
}
|
|
|
|
return bytes;
|
|
}
|