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19aa748be5
We have new broadcast registers on Volta, and we need to generate correct unicast addresses for them so that we can write those registers to context image Add new GR HAL create_priv_addr_table() to do this conversion Set gr_gk20a_create_priv_addr_table() for older chips Set gr_gv11b_create_priv_addr_table() for Volta gr_gv11b_create_priv_addr_table() will use the broadcast flags and then generate appriate list of unicast register for each broadcast register Bug 200398811 Jira NVGPU-556 Change-Id: Id53a9e56106d200fe560ffc93394cc0e976f455f Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1690027 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
58 lines
2.5 KiB
C
58 lines
2.5 KiB
C
/*
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* GV11B/GV100 Graphics Context Pri Register Addressing
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*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef GR_PRI_GV11B_H
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#define GR_PRI_GV11B_H
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/*
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* These convenience macros are generally for use in the management/modificaiton
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* of the context state store for gr/compute contexts.
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*/
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/* Broadcast PMM defines */
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#define NV_PERF_PMMFBP_FBPGS_LTC 0x00250800
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#define NV_PERF_PMMFBP_FBPGS_ROP 0x00250A00
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#define NV_PERF_PMMGPC_GPCGS_GPCTPCA 0x00250000
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#define NV_PERF_PMMGPC_GPCGS_GPCTPCB 0x00250200
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#define NV_PERF_PMMGPC_GPCS 0x00278000
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#define NV_PERF_PMMFBP_FBPS 0x0027C000
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#define NV_PERF_PMMGPCTPCA_DOMAIN_START 2
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#define NV_PERF_PMMFBP_LTC_DOMAIN_START 2
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#define NV_PERF_PMMFBP_ROP_DOMAIN_START 6
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#define NV_PERF_PMMGPC_NUM_DOMAINS 7
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#define NV_PERF_PMMFBP_LTC_NUM_DOMAINS 4
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#define NV_PERF_PMMFBP_ROP_NUM_DOMAINS 2
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#define PRI_PMMGS_ADDR_WIDTH 9
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#define PRI_PMMS_ADDR_WIDTH 14
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/* Get the offset to be added to the chiplet base addr to get the unicast address */
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#define PRI_PMMGS_OFFSET_MASK(addr) ((addr) & ((1 << PRI_PMMGS_ADDR_WIDTH) - 1))
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#define PRI_PMMGS_BASE_ADDR_MASK(addr) ((addr) & (~((1 << PRI_PMMGS_ADDR_WIDTH) - 1)))
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#define PRI_PMMS_ADDR_MASK(addr) ((addr) & ((1 << PRI_PMMS_ADDR_WIDTH) - 1))
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#define PRI_PMMS_BASE_ADDR_MASK(addr) ((addr) & (~((1 << PRI_PMMS_ADDR_WIDTH) - 1)))
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#endif /* GR_PRI_GV11B_H */
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