mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-24 02:22:34 +03:00
1c13da1d29
Changed the enum gmmu_pgsz_gk20a into macros and changed all the instances of it. The enum gmmu_pgsz_gk20a was being used in for loops, where it was compared with an integer. This violates MISRA rule 10.4, which only allows arithmetic operations on operands of the same essential type category. Changing this enum into macro will fix this violation. JIRA NVGPU-993 Change-Id: I6f18b08bc7548093d99e8229378415bcdec749e3 Signed-off-by: Amulya <Amurthyreddy@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1795593 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
82 lines
2.8 KiB
C
82 lines
2.8 KiB
C
/*
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* Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "gk20a/gk20a.h"
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#include "vgpu_subctx_gv11b.h"
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#include <nvgpu/vgpu/vgpu.h>
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#include <nvgpu/vgpu/tegra_vgpu.h>
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#include <nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h>
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int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c)
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{
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struct ctx_header_desc *ctx = &c->ctx_header;
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_alloc_ctx_header_params *p =
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&msg.params.alloc_ctx_header;
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int err;
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msg.cmd = TEGRA_VGPU_CMD_ALLOC_CTX_HEADER;
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msg.handle = vgpu_get_handle(c->g);
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p->ch_handle = c->virt_ctx;
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p->ctx_header_va = __nvgpu_vm_alloc_va(c->vm,
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ctxsw_prog_fecs_header_v(),
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GMMU_PAGE_SIZE_KERNEL);
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if (!p->ctx_header_va) {
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nvgpu_err(c->g, "alloc va failed for ctx_header");
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return -ENOMEM;
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}
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (unlikely(err)) {
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nvgpu_err(c->g, "alloc ctx_header failed err %d", err);
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__nvgpu_vm_free_va(c->vm, p->ctx_header_va,
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GMMU_PAGE_SIZE_KERNEL);
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return err;
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}
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ctx->mem.gpu_va = p->ctx_header_va;
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return err;
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}
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void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c)
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{
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struct ctx_header_desc *ctx = &c->ctx_header;
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struct tegra_vgpu_cmd_msg msg = {};
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struct tegra_vgpu_free_ctx_header_params *p =
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&msg.params.free_ctx_header;
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int err;
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if (ctx->mem.gpu_va) {
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msg.cmd = TEGRA_VGPU_CMD_FREE_CTX_HEADER;
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msg.handle = vgpu_get_handle(c->g);
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p->ch_handle = c->virt_ctx;
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err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
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err = err ? err : msg.ret;
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if (unlikely(err))
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nvgpu_err(c->g, "free ctx_header failed err %d", err);
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__nvgpu_vm_free_va(c->vm, ctx->mem.gpu_va,
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GMMU_PAGE_SIZE_KERNEL);
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ctx->mem.gpu_va = 0;
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}
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}
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