mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
2a2c16af5f
Move all Linux source code files to drivers/gpu/nvgpu/os/linux from drivers/gpu/nvgpu/common/linux. This changes the meaning of common to be OS independent. JIRA NVGPU-598 JIRA NVGPU-601 Change-Id: Ib7f2a43d3688bb0d0b7dcc48469a6783fd988ce9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1747714 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <gk20a/gk20a.h>
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#include <nvgpu/nvlink.h>
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#include <nvgpu/enabled.h>
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#include "module.h"
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#ifdef CONFIG_TEGRA_NVLINK
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int nvgpu_nvlink_read_dt_props(struct gk20a *g)
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{
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struct device_node *np;
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struct nvlink_device *ndev = g->nvlink.priv;
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u32 local_dev_id;
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u32 local_link_id;
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u32 remote_dev_id;
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u32 remote_link_id;
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bool is_master;
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/* Parse DT */
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np = nvgpu_get_node(g);
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if (!np)
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goto fail;
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np = of_get_child_by_name(np, "nvidia,nvlink");
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if (!np)
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goto fail;
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np = of_get_child_by_name(np, "endpoint");
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if (!np)
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goto fail;
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/* Parse DT structure to detect endpoint topology */
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of_property_read_u32(np, "local_dev_id", &local_dev_id);
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of_property_read_u32(np, "local_link_id", &local_link_id);
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of_property_read_u32(np, "remote_dev_id", &remote_dev_id);
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of_property_read_u32(np, "remote_link_id", &remote_link_id);
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is_master = of_property_read_bool(np, "is_master");
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/* Check that we are in dGPU mode */
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if (local_dev_id != NVLINK_ENDPT_GV100) {
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nvgpu_err(g, "Local nvlink device is not dGPU");
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return -EINVAL;
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}
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ndev->is_master = is_master;
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ndev->device_id = local_dev_id;
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ndev->link.link_id = local_link_id;
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ndev->link.remote_dev_info.device_id = remote_dev_id;
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ndev->link.remote_dev_info.link_id = remote_link_id;
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return 0;
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fail:
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nvgpu_info(g, "nvlink endpoint not found or invaling in DT");
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return -ENODEV;
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}
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#endif /* CONFIG_TEGRA_NVLINK */
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void nvgpu_mss_nvlink_init_credits(struct gk20a *g)
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{
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/* MSS_NVLINK_1_BASE */
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void __iomem *soc1 = ioremap(0x01f20010, 4096);
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/* MSS_NVLINK_2_BASE */
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void __iomem *soc2 = ioremap(0x01f40010, 4096);
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/* MSS_NVLINK_3_BASE */
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void __iomem *soc3 = ioremap(0x01f60010, 4096);
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/* MSS_NVLINK_4_BASE */
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void __iomem *soc4 = ioremap(0x01f80010, 4096);
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u32 val;
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nvgpu_log(g, gpu_dbg_info, "init nvlink soc credits");
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val = readl_relaxed(soc1);
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writel_relaxed(val, soc1);
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val = readl_relaxed(soc1 + 4);
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writel_relaxed(val, soc1 + 4);
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val = readl_relaxed(soc2);
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writel_relaxed(val, soc2);
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val = readl_relaxed(soc2 + 4);
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writel_relaxed(val, soc2 + 4);
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val = readl_relaxed(soc3);
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writel_relaxed(val, soc3);
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val = readl_relaxed(soc3 + 4);
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writel_relaxed(val, soc3 + 4);
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val = readl_relaxed(soc4);
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writel_relaxed(val, soc4);
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val = readl_relaxed(soc4 + 4);
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writel_relaxed(val, soc4 + 4);
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}
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