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25aa0f33b1
MISRA Rule 10.4 only allows the usage of arithmetic operations on operands of the same essential type category. Adding "U" at the end of the integer literals to have same type of operands when an arithmetic operation is performed. This fixes violation where an arithmetic operation is performed on signed and unsigned int types. JIRA NVGPU-992 Change-Id: If80c848a47455e631187669b9a67f444dab1e5bc Signed-off-by: Sai Nikhil <snikhil@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1921503 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
129 lines
3.8 KiB
C
129 lines
3.8 KiB
C
/*
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* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/bug.h>
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#include <nvgpu/pmu.h>
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#include <nvgpu/clk_arb.h>
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#include <nvgpu/gk20a.h>
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#include "pmu_perf.h"
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struct perfrpc_pmucmdhandler_params {
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struct nv_pmu_perf_rpc *prpccall;
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u32 success;
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};
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static void perfrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
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void *param, u32 handle, u32 status)
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{
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struct perfrpc_pmucmdhandler_params *phandlerparams =
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(struct perfrpc_pmucmdhandler_params *)param;
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nvgpu_log_info(g, " ");
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if (msg->msg.perf.msg_type != NV_PMU_PERF_MSG_ID_RPC) {
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nvgpu_err(g, "unsupported msg for VFE LOAD RPC %x",
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msg->msg.perf.msg_type);
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return;
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}
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if (phandlerparams->prpccall->b_supported) {
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phandlerparams->success = 1;
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}
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}
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static int pmu_handle_perf_event(struct gk20a *g, void *pmu_msg)
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{
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struct nv_pmu_perf_msg *msg = (struct nv_pmu_perf_msg *)pmu_msg;
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nvgpu_log_fn(g, " ");
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switch (msg->msg_type) {
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case NV_PMU_PERF_MSG_ID_VFE_CALLBACK:
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nvgpu_clk_arb_schedule_vf_table_update(g);
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break;
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default:
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WARN_ON(1);
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break;
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}
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return 0;
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}
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u32 perf_pmu_vfe_load(struct gk20a *g)
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{
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struct pmu_cmd cmd;
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struct pmu_payload payload;
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u32 status;
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u32 seqdesc;
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struct nv_pmu_perf_rpc rpccall;
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struct perfrpc_pmucmdhandler_params handler;
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memset(&payload, 0, sizeof(struct pmu_payload));
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memset(&rpccall, 0, sizeof(struct nv_pmu_perf_rpc));
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memset(&handler, 0, sizeof(struct perfrpc_pmucmdhandler_params));
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/*register call back for future VFE updates*/
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g->ops.pmu_perf.handle_pmu_perf_event = pmu_handle_perf_event;
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rpccall.function = NV_PMU_PERF_RPC_ID_VFE_LOAD;
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rpccall.params.vfe_load.b_load = true;
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cmd.hdr.unit_id = PMU_UNIT_PERF;
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cmd.hdr.size = (u32)sizeof(struct nv_pmu_perf_cmd) +
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(u32)sizeof(struct pmu_hdr);
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cmd.cmd.perf.cmd_type = NV_PMU_PERF_CMD_ID_RPC;
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payload.in.buf = (u8 *)&rpccall;
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payload.in.size = (u32)sizeof(struct nv_pmu_perf_rpc);
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payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
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payload.in.offset = NV_PMU_PERF_CMD_RPC_ALLOC_OFFSET;
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payload.out.buf = (u8 *)&rpccall;
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payload.out.size = (u32)sizeof(struct nv_pmu_perf_rpc);
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payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
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payload.out.offset = NV_PMU_PERF_MSG_RPC_ALLOC_OFFSET;
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handler.prpccall = &rpccall;
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handler.success = 0;
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status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
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PMU_COMMAND_QUEUE_LPQ,
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perfrpc_pmucmdhandler, (void *)&handler,
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&seqdesc, ~0);
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if (status) {
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nvgpu_err(g, "unable to post perf RPC cmd %x",
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cmd.cmd.perf.cmd_type);
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goto done;
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}
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pmu_wait_message_cond(&g->pmu,
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gk20a_get_gr_idle_timeout(g),
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&handler.success, 1);
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if (handler.success == 0U) {
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status = -EINVAL;
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nvgpu_err(g, "rpc call to load VFE failed");
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}
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done:
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return status;
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}
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