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78ad8a23ea
Move the gp106 HW headers to a new directory specially for them: include/nvgpu/hw/gp106 And change the code to include like so: #include <nvgpu/hw/gp106/hw_fb_gp106.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: I76a4ff2e92021150ce65a8843bc12bb614a0e68a Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1280327 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
124 lines
2.8 KiB
C
124 lines
2.8 KiB
C
/*
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* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include "gk20a/gk20a.h"
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#include "gm206/bios_gm206.h"
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#include "bios_gp106.h"
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#include <nvgpu/hw/gp106/hw_gc6_gp106.h>
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static void gp106_init_xmemsel_zm_nv_reg_array(struct gk20a *g, bool *condition,
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u32 reg, u32 stride, u32 count, u32 data_table_offset)
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{
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u8 i;
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u32 data, strap, index;
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if (*condition) {
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strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xf;
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index = g->bios.mem_strap_xlat_tbl_ptr ?
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gm206_bios_read_u8(g, g->bios.mem_strap_xlat_tbl_ptr +
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strap) : strap;
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for (i = 0; i < count; i++) {
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data = gm206_bios_read_u32(g, data_table_offset + ((i *
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g->bios.mem_strap_data_count + index) *
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sizeof(u32)));
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gk20a_writel(g, reg, data);
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reg += stride;
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}
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}
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}
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static void gp106_init_condition(struct gk20a *g, bool *condition,
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u32 condition_id)
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{
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struct condition_entry entry;
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entry.cond_addr = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
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sizeof(entry)*condition_id);
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entry.cond_mask = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
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sizeof(entry)*condition_id + 4);
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entry.cond_compare = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
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sizeof(entry)*condition_id + 8);
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if ((gk20a_readl(g, entry.cond_addr) & entry.cond_mask)
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!= entry.cond_compare) {
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*condition = false;
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}
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}
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static int gp106_execute_script(struct gk20a *g, u32 offset)
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{
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u8 opcode;
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u32 ip;
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u32 operand[8];
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bool condition, end;
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int status = 0;
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ip = offset;
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condition = true;
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end = false;
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while (!end) {
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opcode = gm206_bios_read_u8(g, ip++);
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switch (opcode) {
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case INIT_XMEMSEL_ZM_NV_REG_ARRAY:
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operand[0] = gm206_bios_read_u32(g, ip);
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operand[1] = gm206_bios_read_u8(g, ip+4);
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operand[2] = gm206_bios_read_u8(g, ip+5);
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ip += 6;
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gp106_init_xmemsel_zm_nv_reg_array(g, &condition,
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operand[0], operand[1], operand[2], ip);
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ip += operand[2] * sizeof(u32) *
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g->bios.mem_strap_data_count;
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break;
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case INIT_CONDITION:
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operand[0] = gm206_bios_read_u8(g, ip);
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ip++;
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gp106_init_condition(g, &condition, operand[0]);
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break;
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case INIT_RESUME:
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condition = true;
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break;
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case INIT_DONE:
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end = true;
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break;
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default:
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gk20a_err(dev_from_gk20a(g), "opcode: 0x%02x", opcode);
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end = true;
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status = -EINVAL;
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break;
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}
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}
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return status;
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}
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void gp106_init_bios(struct gpu_ops *gops)
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{
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gm206_init_bios(gops);
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gops->bios.execute_script = gp106_execute_script;
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}
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