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e6b3bb4e6b
Mostly just including necessary includes to make sure that
global function declarations actually match their implementations.
Also work around pointer munging warning:
/build/ddpx/linux/kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/pmu.c: In function 'nvgpu_pmu_process_init_msg':
/build/ddpx/linux/kernel/nvgpu/drivers/gpu/nvgpu/common/pmu/pmu.c:348:4: error: dereferencing type-punned pointer will break strict-aliasing rules [-Werror=strict-aliasing]
(*(u32 *)gid_data.signature == PMU_SHA1_GID_SIGNATURE);
Work around this warning by simply moving the type punning.
This code is certainly dangerous - it assumes the endianness
of the header data is the same as the machine this code is
running on. Apparently it works, though, so this ignores
the warning.
JIRA NVGPU-525
Change-Id: Id704bae7805440bebfad51c8c8365e6d2b7a39eb
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1692454
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
136 lines
4.9 KiB
C
136 lines
4.9 KiB
C
/*
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* GP10B Therm
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*
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* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "gk20a/gk20a.h"
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#include "therm_gp10b.h"
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#include <nvgpu/soc.h>
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#include <nvgpu/hw/gp10b/hw_therm_gp10b.h>
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int gp10b_init_therm_setup_hw(struct gk20a *g)
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{
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u32 v;
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gk20a_dbg_fn("");
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/* program NV_THERM registers */
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gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() |
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therm_use_a_ext_therm_1_enable_f() |
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therm_use_a_ext_therm_2_enable_f());
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gk20a_writel(g, therm_evt_ext_therm_0_r(),
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therm_evt_ext_therm_0_slow_factor_f(0x2));
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gk20a_writel(g, therm_evt_ext_therm_1_r(),
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therm_evt_ext_therm_1_slow_factor_f(0x6));
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gk20a_writel(g, therm_evt_ext_therm_2_r(),
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therm_evt_ext_therm_2_slow_factor_f(0xe));
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gk20a_writel(g, therm_grad_stepping_table_r(0),
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therm_grad_stepping_table_slowdown_factor0_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) |
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therm_grad_stepping_table_slowdown_factor1_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) |
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therm_grad_stepping_table_slowdown_factor2_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) |
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therm_grad_stepping_table_slowdown_factor3_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
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therm_grad_stepping_table_slowdown_factor4_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
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gk20a_writel(g, therm_grad_stepping_table_r(1),
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therm_grad_stepping_table_slowdown_factor0_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
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therm_grad_stepping_table_slowdown_factor1_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
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therm_grad_stepping_table_slowdown_factor2_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
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therm_grad_stepping_table_slowdown_factor3_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) |
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therm_grad_stepping_table_slowdown_factor4_f(
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therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()));
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v = gk20a_readl(g, therm_clk_timing_r(0));
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v |= therm_clk_timing_grad_slowdown_enabled_f();
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gk20a_writel(g, therm_clk_timing_r(0), v);
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v = gk20a_readl(g, therm_config2_r());
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v |= therm_config2_grad_enable_f(1);
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v |= therm_config2_slowdown_factor_extended_f(1);
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gk20a_writel(g, therm_config2_r(), v);
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gk20a_writel(g, therm_grad_stepping1_r(),
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therm_grad_stepping1_pdiv_duration_f(32));
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v = gk20a_readl(g, therm_grad_stepping0_r());
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v |= therm_grad_stepping0_feature_enable_f();
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gk20a_writel(g, therm_grad_stepping0_r(), v);
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return 0;
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}
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int gp10b_elcg_init_idle_filters(struct gk20a *g)
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{
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u32 gate_ctrl, idle_filter;
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u32 engine_id;
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u32 active_engine_id = 0;
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struct fifo_gk20a *f = &g->fifo;
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gk20a_dbg_fn("");
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for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
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active_engine_id = f->active_engines_list[engine_id];
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gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
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if (nvgpu_platform_is_simulation(g)) {
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_delay_after_m(),
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therm_gate_ctrl_eng_delay_after_f(4));
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}
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/* 2 * (1 << 9) = 1024 clks */
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_idle_filt_exp_m(),
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therm_gate_ctrl_eng_idle_filt_exp_f(9));
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_idle_filt_mant_m(),
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therm_gate_ctrl_eng_idle_filt_mant_f(2));
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gate_ctrl = set_field(gate_ctrl,
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therm_gate_ctrl_eng_delay_before_m(),
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therm_gate_ctrl_eng_delay_before_f(4));
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gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
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}
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/* default fecs_idle_filter to 0 */
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idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
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idle_filter &= ~therm_fecs_idle_filter_value_m();
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gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
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/* default hubmmu_idle_filter to 0 */
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idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
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idle_filter &= ~therm_hubmmu_idle_filter_value_m();
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gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
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gk20a_dbg_fn("done");
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return 0;
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}
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