mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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2a865e3aad
This patch adds nvenc support for TU104 - Fetch engine/dev info for nvenc - Falcon NS boot (fw loading) support - Engine context creation for nvenc - Skip golden image for multimedia engines - Avoid subctx for nvenc as it is a non-VEID engine - Job submission/flow changes for nvenc - Code refactoring to scale up the support for other multimedia engines in future. Bug 3763551 Change-Id: I03d4e731ebcef456bcc5ce157f3aa39883270dc0 Signed-off-by: Santosh BS <santoshb@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859416 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
112 lines
3.4 KiB
C
112 lines
3.4 KiB
C
/*
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* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/falcon.h>
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#include "falcon_sw_gk20a.h"
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#include "falcon_sw_tu104.h"
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void tu104_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
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{
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struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops =
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&flcn->flcn_engine_dep_ops;
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struct gk20a *g = flcn->g;
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gk20a_falcon_engine_dependency_ops(flcn);
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switch (flcn->flcn_id) {
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case FALCON_ID_GSPLITE:
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flcn_eng_dep_ops->reset_eng = g->ops.gsp.gsp_reset;
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flcn_eng_dep_ops->setup_bootstrap_config =
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g->ops.gsp.falcon_setup_boot_config;
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break;
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case FALCON_ID_SEC2:
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flcn_eng_dep_ops->reset_eng = g->ops.sec2.sec2_reset;
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flcn_eng_dep_ops->setup_bootstrap_config =
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g->ops.sec2.flcn_setup_boot_config;
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flcn_eng_dep_ops->copy_to_emem = g->ops.sec2.sec2_copy_to_emem;
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flcn_eng_dep_ops->copy_from_emem =
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g->ops.sec2.sec2_copy_from_emem;
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break;
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case FALCON_ID_NVENC:
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flcn_eng_dep_ops->setup_bootstrap_config =
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g->ops.nvenc.setup_boot_config;
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break;
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default:
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flcn_eng_dep_ops->reset_eng = NULL;
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break;
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}
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}
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void tu104_falcon_sw_init(struct nvgpu_falcon *flcn)
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{
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struct gk20a *g = flcn->g;
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switch (flcn->flcn_id) {
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case FALCON_ID_GSPLITE:
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flcn->flcn_base = g->ops.gsp.falcon_base_addr();
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = false;
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break;
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case FALCON_ID_SEC2:
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flcn->flcn_base = g->ops.sec2.falcon_base_addr();
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = true;
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flcn->emem_supported = true;
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break;
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case FALCON_ID_MINION:
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flcn->flcn_base = g->ops.nvlink.minion.base_addr(g);
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = true;
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break;
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case FALCON_ID_NVDEC:
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flcn->flcn_base = g->ops.nvdec.falcon_base_addr();
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = true;
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break;
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case FALCON_ID_NVENC:
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flcn->flcn_base = g->ops.nvenc.base_addr();
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flcn->is_falcon_supported = true;
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flcn->is_interrupt_enabled = true;
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break;
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default:
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/*
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* set false to inherit falcon support
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* from previous chips HAL
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*/
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flcn->is_falcon_supported = false;
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break;
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}
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if (flcn->is_falcon_supported) {
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tu104_falcon_engine_dependency_ops(flcn);
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} else {
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/*
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* Forward call to previous chip's SW init
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* to fetch info for requested
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* falcon as no changes between
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* current & previous chips.
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*/
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gk20a_falcon_sw_init(flcn);
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}
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}
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