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2a865e3aad
This patch adds nvenc support for TU104 - Fetch engine/dev info for nvenc - Falcon NS boot (fw loading) support - Engine context creation for nvenc - Skip golden image for multimedia engines - Avoid subctx for nvenc as it is a non-VEID engine - Job submission/flow changes for nvenc - Code refactoring to scale up the support for other multimedia engines in future. Bug 3763551 Change-Id: I03d4e731ebcef456bcc5ce157f3aa39883270dc0 Signed-off-by: Santosh BS <santoshb@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2859416 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
116 lines
4.0 KiB
C
116 lines
4.0 KiB
C
/*
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* Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/io.h>
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#include <nvgpu/multimedia.h>
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#include "nvenc_tu104.h"
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#include <nvgpu/hw/tu104/hw_pnvenc_tu104.h>
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u32 tu104_nvenc_base_addr(void)
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{
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return pnvenc_falcon_irqsset_r(0);
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}
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void tu104_nvenc_setup_boot_config(struct gk20a *g)
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{
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u32 data = 0;
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data = nvgpu_readl(g, pnvenc_fbif_ctl_r());
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data |= pnvenc_fbif_ctl_allow_phys_no_ctx_allow_f();
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nvgpu_writel(g, pnvenc_fbif_ctl_r(), data);
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/* Setup aperture (physical) for ucode loading */
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data = nvgpu_readl(g, pnvenc_fbif_transcfg_r(UCODE_DMA_ID));
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data |= pnvenc_fbif_transcfg_mem_type_physical_f() |
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pnvenc_fbif_transcfg_target_noncoherent_sysmem_f();
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nvgpu_writel(g, pnvenc_fbif_transcfg_r(UCODE_DMA_ID), data);
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/* Enable the context interface */
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nvgpu_writel(g, pnvenc_falcon_itfen_r(),
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nvgpu_readl(g, pnvenc_falcon_itfen_r()) |
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pnvenc_falcon_itfen_ctxen_enable_f());
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}
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void tu104_nvenc_halt_engine(struct gk20a *g)
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{
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u32 data;
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data = nvgpu_readl(g, pnvenc_falcon_engctl_r());
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data |= pnvenc_falcon_engctl_stallreq_true_f();
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nvgpu_writel(g, pnvenc_falcon_engctl_r(), data);
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data = nvgpu_readl(g, pnvenc_falcon_engctl_r());
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if (pnvenc_falcon_engctl_stallack_v(data) == 0U) {
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nvgpu_err(g, "NVENC engine is not idle while reset");
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}
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}
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void tu104_nvenc_set_irq_regs(struct gk20a *g, struct nvgpu_falcon *flcn)
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{
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u32 intr_mask;
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u32 intr_dest;
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/* dest 0=falcon, 1=host; level 0=irq0, 1=irq1 */
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intr_dest = pnvenc_falcon_irqdest_host_gptmr_f(0) |
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pnvenc_falcon_irqdest_host_wdtmr_f(1) |
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pnvenc_falcon_irqdest_host_mthd_f(0) |
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pnvenc_falcon_irqdest_host_ctxsw_f(0) |
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pnvenc_falcon_irqdest_host_halt_f(1) |
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pnvenc_falcon_irqdest_host_exterr_f(1) |
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pnvenc_falcon_irqdest_host_swgen0_f(1) |
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pnvenc_falcon_irqdest_host_swgen1_f(1) |
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pnvenc_falcon_irqdest_host_ext_f(0xff) |
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pnvenc_falcon_irqdest_target_gptmr_f(0) |
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pnvenc_falcon_irqdest_target_wdtmr_f(0) |
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pnvenc_falcon_irqdest_target_mthd_f(0) |
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pnvenc_falcon_irqdest_target_ctxsw_f(0) |
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pnvenc_falcon_irqdest_target_halt_f(0) |
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pnvenc_falcon_irqdest_target_exterr_f(0) |
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pnvenc_falcon_irqdest_target_swgen0_f(0) |
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pnvenc_falcon_irqdest_target_swgen1_f(0) |
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pnvenc_falcon_irqdest_target_ext_f(0);
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/* 0=disable, 1=enable */
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intr_mask = pnvenc_falcon_irqmset_gptmr_f(0) |
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pnvenc_falcon_irqmset_wdtmr_f(1) |
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pnvenc_falcon_irqmset_mthd_f(0) |
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pnvenc_falcon_irqmset_ctxsw_f(0) |
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pnvenc_falcon_irqmset_halt_f(1) |
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pnvenc_falcon_irqmset_exterr_f(0) |
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pnvenc_falcon_irqmset_swgen0_f(1) |
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pnvenc_falcon_irqmset_swgen1_f(1) |
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pnvenc_falcon_irqmset_ext_f(0xff);
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g->ops.falcon.set_irq(flcn, true, intr_mask, intr_dest);
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}
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void tu104_nvenc_interface_enable(struct gk20a *g)
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{
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u32 itfen;
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itfen = nvgpu_readl(g, pnvenc_falcon_itfen_r()) |
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pnvenc_falcon_itfen_ctxen_enable_f() |
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pnvenc_falcon_itfen_mthden_enable_f();
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nvgpu_writel(g, pnvenc_falcon_itfen_r(), itfen);
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}
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