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17486ec1f6
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct channel_gk20a to struct nvgpu_channel Jira NVGPU-3248 Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2112424 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
77 lines
2.0 KiB
C
77 lines
2.0 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_GR_INTR_PRIV_H
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#define NVGPU_GR_INTR_PRIV_H
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#include <nvgpu/types.h>
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#include <nvgpu/lock.h>
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struct nvgpu_channel;
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struct nvgpu_gr_intr_info {
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u32 notify;
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u32 semaphore;
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u32 illegal_notify;
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u32 illegal_method;
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u32 illegal_class;
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u32 fecs_error;
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u32 class_error;
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u32 fw_method;
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u32 exception;
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};
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struct nvgpu_gr_tpc_exception {
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bool tex_exception;
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bool sm_exception;
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bool mpc_exception;
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};
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struct nvgpu_gr_isr_data {
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u32 addr;
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u32 data_lo;
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u32 data_hi;
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u32 curr_ctx;
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struct nvgpu_channel *ch;
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u32 offset;
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u32 sub_chan;
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u32 class_num;
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};
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struct gr_channel_map_tlb_entry {
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u32 curr_ctx;
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u32 chid;
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u32 tsgid;
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};
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struct nvgpu_gr_intr {
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#define GR_CHANNEL_MAP_TLB_SIZE 2U /* must of power of 2 */
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struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE];
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u32 channel_tlb_flush_index;
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struct nvgpu_spinlock ch_tlb_lock;
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};
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#endif /* NVGPU_GR_INTR_PRIV_H */
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