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17486ec1f6
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct channel_gk20a to struct nvgpu_channel Jira NVGPU-3248 Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2112424 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
106 lines
2.9 KiB
C
106 lines
2.9 KiB
C
/*
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* GK20A syncpt cmdbuf
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*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/nvgpu_mem.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/channel.h>
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#include "syncpt_cmdbuf_gk20a.h"
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void gk20a_syncpt_add_wait_cmd(struct gk20a *g,
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struct priv_cmd_entry *cmd, u32 off,
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u32 id, u32 thresh, u64 gpu_va)
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{
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nvgpu_log_fn(g, " ");
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off = cmd->off + off;
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/* syncpoint_a */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001CU);
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/* payload */
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nvgpu_mem_wr32(g, cmd->mem, off++, thresh);
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/* syncpoint_b */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001DU);
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/* syncpt_id, switch_en, wait */
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nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8U) | 0x10U);
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}
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u32 gk20a_syncpt_get_wait_cmd_size(void)
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{
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return 4U;
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}
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u32 gk20a_syncpt_get_incr_per_release(void)
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{
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return 2U;
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}
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void gk20a_syncpt_add_incr_cmd(struct gk20a *g,
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bool wfi_cmd, struct priv_cmd_entry *cmd,
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u32 id, u64 gpu_va)
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{
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u32 off = cmd->off;
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nvgpu_log_fn(g, " ");
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if (wfi_cmd) {
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/* wfi */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001EU);
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/* handle, ignored */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x00000000U);
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}
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/* syncpoint_a */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001CU);
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/* payload, ignored */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0U);
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/* syncpoint_b */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001DU);
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/* syncpt_id, incr */
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nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8U) | 0x1U);
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/* syncpoint_b */
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nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001DU);
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/* syncpt_id, incr */
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nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8U) | 0x1U);
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}
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u32 gk20a_syncpt_get_incr_cmd_size(bool wfi_cmd)
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{
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if (wfi_cmd) {
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return 8U;
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} else {
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return 6U;
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}
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}
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void gk20a_syncpt_free_buf(struct nvgpu_channel *c,
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struct nvgpu_mem *syncpt_buf)
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{
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}
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int gk20a_syncpt_alloc_buf(struct nvgpu_channel *c,
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u32 syncpt_id, struct nvgpu_mem *syncpt_buf)
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{
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return 0;
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}
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