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6c2c4181ae
There are many miscellaneous HALs for various MM related functionality. This patch aims to migrate all the remaining MM code from the <chip>/ mm_<chip>.[ch] files in HAL files under hal/. Much of this is fairly straightforward copy/paste and updates to the HAL init files. The exception to that is the move of the left over gv11b MMU fault handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in a subsequent patch. JIRA NVGPU-2042 Change-Id: I12896de865d890a61afbcb71159cff486119ffb8 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2109050 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
/*
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* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __COMMON_LINUX_DMABUF_H__
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#define __COMMON_LINUX_DMABUF_H__
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#include <nvgpu/comptags.h>
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#include <nvgpu/list.h>
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#include <nvgpu/lock.h>
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#include <nvgpu/gmmu.h>
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struct sg_table;
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struct dma_buf;
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struct dma_buf_attachment;
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struct device;
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struct gk20a;
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struct gk20a_buffer_state {
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struct nvgpu_list_node list;
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/* The valid compbits and the fence must be changed atomically. */
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struct nvgpu_mutex lock;
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/* Offset of the surface within the dma-buf whose state is
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* described by this struct (one dma-buf can contain multiple
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* surfaces with different states). */
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size_t offset;
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/* A bitmask of valid sets of compbits (0 = uncompressed). */
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u32 valid_compbits;
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/* The ZBC color used on this buffer. */
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u32 zbc_color;
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/* This struct reflects the state of the buffer when this
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* fence signals. */
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struct nvgpu_fence_type *fence;
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};
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static inline struct gk20a_buffer_state *
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gk20a_buffer_state_from_list(struct nvgpu_list_node *node)
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{
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return (struct gk20a_buffer_state *)
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((uintptr_t)node - offsetof(struct gk20a_buffer_state, list));
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};
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struct gk20a_dmabuf_priv {
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struct nvgpu_mutex lock;
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struct gk20a *g;
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struct gk20a_comptag_allocator *comptag_allocator;
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struct gk20a_comptags comptags;
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struct dma_buf_attachment *attach;
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struct sg_table *sgt;
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int pin_count;
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struct nvgpu_list_node states;
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u64 buffer_id;
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};
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struct sg_table *gk20a_mm_pin(struct device *dev, struct dma_buf *dmabuf,
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struct dma_buf_attachment **attachment);
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void gk20a_mm_unpin(struct device *dev, struct dma_buf *dmabuf,
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struct dma_buf_attachment *attachment,
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struct sg_table *sgt);
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int gk20a_dmabuf_alloc_drvdata(struct dma_buf *dmabuf, struct device *dev);
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int gk20a_dmabuf_get_state(struct dma_buf *dmabuf, struct gk20a *g,
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u64 offset, struct gk20a_buffer_state **state);
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#endif
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