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6299b00beb
This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt handling support for gm206 GPU family 5) Added generic mechanism to identify the CE engine pri_base address for gm206 (CE0, CE1 and CE2) 6) Removed hard coded engine_id logic and made generic way 7) Code cleanup for readability JIRA DNVGPU-26 Change-Id: I2c3846c40bcc8d10c2dfb225caa4105fc9123b65 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1155963 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
108 lines
3.1 KiB
C
108 lines
3.1 KiB
C
/*
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* GM206 Copy Engine.
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*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program.
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*/
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/*TODO: remove uncecessary */
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#include "gk20a/gk20a.h"
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#include "ce_gm206.h"
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/*TODO: remove uncecessary */
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/scatterlist.h>
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#include <trace/events/gk20a.h>
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#include <linux/dma-mapping.h>
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#include <linux/nvhost.h>
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#include "gk20a/debug_gk20a.h"
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#include "gk20a/semaphore_gk20a.h"
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#include "hw_ce2_gm206.h"
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#include "hw_pbdma_gm206.h"
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#include "hw_ccsr_gm206.h"
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#include "hw_ram_gm206.h"
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#include "hw_top_gm206.h"
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#include "hw_mc_gm206.h"
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#include "hw_gr_gm206.h"
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/* TODO: We need generic way for query the intr_status register offset.
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* As of now, there is no way to query this information from dev_ceN_pri.h */
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#define COP_INTR_STATUS_OFFSET 0x908
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static u32 ce_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id)
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{
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gk20a_dbg(gpu_dbg_intr, "ce non-blocking pipe interrupt\n");
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return ce2_intr_status_nonblockpipe_pending_f();
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}
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static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id)
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{
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gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n");
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return ce2_intr_status_blockpipe_pending_f();
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}
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static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id)
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{
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gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n");
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return ce2_intr_status_launcherr_pending_f();
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}
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void gm206_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ce_intr_status_reg = (pri_base + COP_INTR_STATUS_OFFSET);
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u32 ce_intr = gk20a_readl(g, ce_intr_status_reg);
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u32 clear_intr = 0;
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gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id);
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/* clear blocking interrupts: they exibit broken behavior */
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if (ce_intr & ce2_intr_status_blockpipe_pending_f())
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clear_intr |= ce_blockpipe_isr(g, ce_intr, inst_id);
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if (ce_intr & ce2_intr_status_launcherr_pending_f())
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clear_intr |= ce_launcherr_isr(g, ce_intr, inst_id);
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gk20a_writel(g, ce_intr_status_reg, clear_intr);
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return;
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}
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void gm206_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base)
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{
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u32 ce_intr_status_reg = (pri_base + COP_INTR_STATUS_OFFSET);
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u32 ce_intr = gk20a_readl(g, ce_intr_status_reg);
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gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id);
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if (ce_intr & ce2_intr_status_nonblockpipe_pending_f()) {
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gk20a_writel(g, ce_intr_status_reg,
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ce_nonblockpipe_isr(g, ce_intr, inst_id));
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/* wake threads waiting in this channel */
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gk20a_channel_semaphore_wakeup(g, true);
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}
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return;
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}
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void gm206_init_ce(struct gpu_ops *gops)
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{
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gops->ce2.isr_stall = gm206_ce_isr;
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gops->ce2.isr_nonstall = gm206_ce_nonstall_isr;
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}
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