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6299b00beb
This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt handling support for gm206 GPU family 5) Added generic mechanism to identify the CE engine pri_base address for gm206 (CE0, CE1 and CE2) 6) Removed hard coded engine_id logic and made generic way 7) Code cleanup for readability JIRA DNVGPU-26 Change-Id: I2c3846c40bcc8d10c2dfb225caa4105fc9123b65 Signed-off-by: Lakshmanan M <lm@nvidia.com> Reviewed-on: http://git-master/r/1155963 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
34 lines
1000 B
C
34 lines
1000 B
C
/*
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* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/delay.h>
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#include <linux/types.h>
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#include "gk20a/gk20a.h"
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#include "gm20b/fifo_gm20b.h"
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#include "fifo_gm206.h"
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#include "hw_ccsr_gm206.h"
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#include "hw_fifo_gm206.h"
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static u32 gm206_fifo_get_num_fifos(struct gk20a *g)
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{
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return ccsr_channel__size_1_v();
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}
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void gm206_init_fifo(struct gpu_ops *gops)
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{
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gm20b_init_fifo(gops);
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gops->fifo.get_num_fifos = gm206_fifo_get_num_fifos;
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gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v;
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}
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