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a21e56d584
Add virtualized support for NUM_VSMS and VSMS_MAPPING ioctls. This requires adding an attribute request for the RM server, GPC0_TPC_COUNT JIRASW EVLR-253 Change-Id: Icaab4fadbbc9eab5d00cf78132928686944162df Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: http://git-master/r/1130615 (cherry picked from commit 78514079382b0de48457db340e3479e99a012040) Reviewed-on: http://git-master/r/1133865 (cherry picked from commit 27a8e645e2787a43d0073f0be6e8f64c0f183228) Reviewed-on: http://git-master/r/1122553 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
80 lines
2.1 KiB
C
80 lines
2.1 KiB
C
/*
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* Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/kernel.h>
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#include "gk20a/hw_gr_gk20a.h"
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#include "gk20a/gk20a.h"
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#include "vgpu/vgpu.h"
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#include "vgpu_gr_gk20a.h"
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static void vgpu_gk20a_detect_sm_arch(struct gk20a *g)
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{
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struct gk20a_platform *platform = gk20a_get_platform(g->dev);
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u32 v = 0, raw_version, version = 0;
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gk20a_dbg_fn("");
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if (vgpu_get_attribute(platform->virt_handle,
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TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH, &v))
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gk20a_err(dev_from_gk20a(g), "failed to retrieve SM arch");
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raw_version = gr_gpc0_tpc0_sm_arch_spa_version_v(v);
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if (raw_version == gr_gpc0_tpc0_sm_arch_spa_version_smkepler_lp_v())
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version = 0x320; /* SM 3.2 */
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else
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gk20a_err(dev_from_gk20a(g), "Unknown SM version 0x%x",
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raw_version);
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/* on Kepler, SM version == SPA version */
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g->gpu_characteristics.sm_arch_spa_version = version;
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g->gpu_characteristics.sm_arch_sm_version = version;
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g->gpu_characteristics.sm_arch_warp_count =
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gr_gpc0_tpc0_sm_arch_warp_count_v(v);
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}
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static int vgpu_gk20a_init_fs_state(struct gk20a *g)
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{
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struct gr_gk20a *gr = &g->gr;
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u32 tpc_index, gpc_index;
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u32 sm_id = 0;
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gk20a_dbg_fn("");
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for (tpc_index = 0; tpc_index < gr->max_tpc_per_gpc_count;
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tpc_index++) {
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for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) {
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if (tpc_index < gr->gpc_tpc_count[gpc_index]) {
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g->gr.sm_to_cluster[sm_id].tpc_index =
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tpc_index;
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g->gr.sm_to_cluster[sm_id].gpc_index =
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gpc_index;
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sm_id++;
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}
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}
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}
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gr->no_of_sm = sm_id;
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return 0;
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}
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void vgpu_gk20a_init_gr_ops(struct gpu_ops *gops)
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{
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gops->gr.detect_sm_arch = vgpu_gk20a_detect_sm_arch;
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gops->gr.init_fs_state = vgpu_gk20a_init_fs_state;
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}
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