mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
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d707c5a444
- make tsg_gk20a.c call HAL for enable/disable channels - add preempt_tsg HAL callbacks - add tsg bind/unbind channel HAL callbacks - add according tsg callbacks for vgpu Bug 1702773 JIRA VFND-1003 Change-Id: I2cba74b3ebd3920ef09219a168e6433d9574dbe8 Signed-off-by: Richard Zhao <rizhao@nvidia.com> Reviewed-on: http://git-master/r/1144932 (cherry picked from commit c3787de7d38651d46969348f5acae2ba86b31ec7) Reviewed-on: http://git-master/r/1126942 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
152 lines
4.1 KiB
C
152 lines
4.1 KiB
C
/*
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* Virtualized GPU Interfaces
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*
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* Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _VIRT_H_
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#define _VIRT_H_
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#include <linux/tegra_gr_comm.h>
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#include <linux/tegra_vgpu.h>
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#include "gk20a/gk20a.h"
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#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
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int vgpu_pm_prepare_poweroff(struct device *dev);
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int vgpu_pm_finalize_poweron(struct device *dev);
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int vgpu_probe(struct platform_device *dev);
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int vgpu_remove(struct platform_device *dev);
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u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size);
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int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info);
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int vgpu_gr_nonstall_isr(struct gk20a *g,
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struct tegra_vgpu_gr_nonstall_intr_info *info);
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int vgpu_gr_alloc_gr_ctx(struct gk20a *g,
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struct gr_ctx_desc **__gr_ctx,
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struct vm_gk20a *vm,
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u32 class,
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u32 flags);
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void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
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struct gr_ctx_desc *gr_ctx);
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int vgpu_gr_init_ctx_state(struct gk20a *g);
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int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info);
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int vgpu_fifo_nonstall_isr(struct gk20a *g,
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struct tegra_vgpu_fifo_nonstall_intr_info *info);
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int vgpu_ce2_nonstall_isr(struct gk20a *g,
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struct tegra_vgpu_ce2_nonstall_intr_info *info);
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void vgpu_init_fifo_ops(struct gpu_ops *gops);
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void vgpu_init_gr_ops(struct gpu_ops *gops);
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void vgpu_init_ltc_ops(struct gpu_ops *gops);
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void vgpu_init_mm_ops(struct gpu_ops *gops);
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void vgpu_init_debug_ops(struct gpu_ops *gops);
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void vgpu_init_tsg_ops(struct gpu_ops *gops);
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int vgpu_init_mm_support(struct gk20a *g);
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int vgpu_init_gr_support(struct gk20a *g);
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int vgpu_init_fifo_support(struct gk20a *g);
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int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value);
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int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
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size_t size_out);
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void vgpu_init_hal_common(struct gk20a *g);
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int vgpu_gk20a_init_hal(struct gk20a *g);
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int vgpu_gm20b_init_hal(struct gk20a *g);
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void vgpu_dbg_init(void);
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#else
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static inline int vgpu_pm_prepare_poweroff(struct device *dev)
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{
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return -ENOSYS;
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}
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static inline int vgpu_pm_finalize_poweron(struct device *dev)
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{
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return -ENOSYS;
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}
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static inline int vgpu_probe(struct platform_device *dev)
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{
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return -ENOSYS;
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}
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static inline int vgpu_remove(struct platform_device *dev)
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{
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return -ENOSYS;
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}
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static inline u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt,
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u64 size)
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{
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return 0;
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}
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static inline int vgpu_gr_isr(struct gk20a *g,
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struct tegra_vgpu_gr_intr_info *info)
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{
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return 0;
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}
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static inline int vgpu_gr_alloc_gr_ctx(struct gk20a *g,
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struct gr_ctx_desc **__gr_ctx,
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struct vm_gk20a *vm,
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u32 class,
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u32 flags)
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{
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return -ENOSYS;
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}
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static inline void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
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struct gr_ctx_desc *gr_ctx)
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{
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}
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static inline int vgpu_gr_init_ctx_state(struct gk20a *g)
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{
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return -ENOSYS;
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}
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static inline int vgpu_fifo_isr(struct gk20a *g,
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struct tegra_vgpu_fifo_intr_info *info)
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{
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return 0;
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}
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static inline void vgpu_init_fifo_ops(struct gpu_ops *gops)
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{
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}
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static inline void vgpu_init_gr_ops(struct gpu_ops *gops)
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{
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}
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static inline void vgpu_init_ltc_ops(struct gpu_ops *gops)
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{
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}
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static inline void vgpu_init_mm_ops(struct gpu_ops *gops)
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{
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}
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static inline void vgpu_init_debug_ops(struct gpu_ops *gops)
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{
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}
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static inline int vgpu_init_mm_support(struct gk20a *g)
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{
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return -ENOSYS;
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}
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static inline int vgpu_init_gr_support(struct gk20a *g)
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{
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return -ENOSYS;
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}
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static inline int vgpu_init_fifo_support(struct gk20a *g)
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{
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return -ENOSYS;
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}
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static inline int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value)
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{
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return -ENOSYS;
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}
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static inline int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
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size_t size_out)
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{
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return -ENOSYS;
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}
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#endif
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#endif
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