smadhavan c7a3b6db10 gpu: nvgpu: Fix MISRA 15.6 violations ...

MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces by introducing the braces.

JIRA NVGPU-671

Change-Id: I8046a09fa7ffc74c3d737ba57132a0a9ae2ff195
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797699
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2018-09-12 05:36:04 -07:00

..

perf.c

gpu: nvgpu: Fix MISRA 15.6 violations

2018-09-12 05:36:04 -07:00

perf.h

gpu:nvgpu: Update vfe_load for GV100

2018-06-14 06:44:06 -07:00

vfe_equ.c

gpu: nvgpu: Fix MISRA 15.6 violations

2018-09-12 05:36:04 -07:00

vfe_equ.h

gpu: nvgpu: cleanup return types for MISRA 10.3

2018-09-06 21:33:50 -07:00

vfe_var.c

gpu: nvgpu: Fix MISRA 15.6 violations

2018-09-12 05:36:04 -07:00

vfe_var.h

gpu: nvgpu: cleanup return types for MISRA 10.3

2018-09-06 21:33:50 -07:00