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2d3ba5478d
- Clocks params update as per r370 JIRA DNVGPU-116 Change-Id: I0aaa1e275aaa2027f2839f3fe24c9aee3e14fd8d Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1212827 (cherry picked from commit 54df6ad9668d46dffb5b9d03265948a47611ff13) Reviewed-on: http://git-master/r/1227288 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit
96 lines
2.4 KiB
C
96 lines
2.4 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _CLKDOMAIN_H_
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#define _CLKDOMAIN_H_
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#include "ctrl/ctrlclk.h"
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#include "ctrl/ctrlboardobj.h"
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#include "pmuif/gpmuifclk.h"
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#include "boardobj/boardobjgrp_e32.h"
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#include "boardobj/boardobjgrpmask.h"
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struct clk_domains;
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struct clk_domain;
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/*data and function definition to talk to driver*/
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u32 clk_domain_sw_setup(struct gk20a *g);
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u32 clk_domain_pmu_setup(struct gk20a *g);
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typedef u32 clkproglink(struct gk20a *g, struct clk_pmupstate *pclk,
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struct clk_domain *pdomain);
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struct clk_domains {
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struct boardobjgrp_e32 super;
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u8 n_num_entries;
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u8 version;
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bool b_enforce_vf_monotonicity;
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bool b_enforce_vf_smoothening;
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u32 vbios_domains;
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struct boardobjgrpmask_e32 prog_domains_mask;
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struct boardobjgrpmask_e32 master_domains_mask;
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u16 cntr_sampling_periodms;
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struct ctrl_clk_clk_delta deltas;
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struct clk_domain *ordered_noise_aware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
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struct clk_domain *ordered_noise_unaware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
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};
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struct clk_domain {
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struct boardobj super;
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u32 api_domain;
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u32 part_mask;
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u8 domain;
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u8 perf_domain_index;
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u8 perf_domain_grp_idx;
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u8 ratio_domain;
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u8 usage;
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clkproglink *clkdomainclkproglink;
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};
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struct clk_domain_3x {
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struct clk_domain super;
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bool b_noise_aware_capable;
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};
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struct clk_domain_3x_fixed {
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struct clk_domain_3x super;
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u16 freq_mhz;
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};
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struct clk_domain_3x_prog {
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struct clk_domain_3x super;
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u8 clk_prog_idx_first;
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u8 clk_prog_idx_last;
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u8 noise_unaware_ordering_index;
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u8 noise_aware_ordering_index;
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bool b_force_noise_unaware_ordering;
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int factory_offset_khz;
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short freq_delta_min_mhz;
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short freq_delta_max_mhz;
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struct ctrl_clk_clk_delta deltas;
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};
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struct clk_domain_3x_master {
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struct clk_domain_3x_prog super;
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u32 slave_idxs_mask;
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};
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struct clk_domain_3x_slave {
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struct clk_domain_3x_prog super;
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u8 master_idx;
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};
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u32 clk_domain_clk_prog_link(struct gk20a *g, struct clk_pmupstate *pclk);
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#endif
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