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Add support for accessing Event Queue for non-exclusive users. Allows, non-exclusive users to open Event Queues before exclusive users. Non-Exclusive users can only use the Event Queue in a read-only mode. Add VM_SHARED for Event Queues across all users instead of just Read-Only users. Event queues are shared with multiple processes and as such require VM_SHARED across all users(exclusive and observers). Jira NVGPU-8608 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Change-Id: Id9733c2511ded6f06dd9feea880005bdc92e51a0 Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2745083 Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> GVS: Gerrit_Virtual_Submit
75 lines
2.4 KiB
C
75 lines
2.4 KiB
C
/*
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* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef NVGPU_DMABUF_NVS_H
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#define NVGPU_DMABUF_NVS_H
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#include <nvgpu/types.h>
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#include <nvgpu/list.h>
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struct dma_buf;
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struct gk20a;
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struct nvgpu_nvs_linux_buf_priv {
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/* This is used to temporarily contain the dmabuf for handling failure */
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struct dma_buf *dmabuf_temp;
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bool read_only;
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u32 mapped_ref;
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struct nvgpu_list_node list_mapped_user_vmas;
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};
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struct nvgpu_nvs_domain_ctrl_fifo_user_vma {
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bool read_only;
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struct nvgpu_nvs_ctrl_queue *buf;
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struct vm_area_struct *vma;
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struct nvgpu_list_node node;
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};
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int nvgpu_nvs_get_buf(struct gk20a *g, struct nvgpu_nvs_ctrl_queue *buf,
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bool read_only);
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/**
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* @brief Construct a buffer for use as a shared message passing
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* queue between user and backend scheduler. Function is
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* not safe from concurrent access by multiple external
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* users. Must be invoked between the calls of
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* nvgpu_nvs_ctrl_fifo_lock_queues() and
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* nvgpu_nvs_ctrl_fifo_unlock_queues().
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*
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* @param g instance of struct gk20a.
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* @param buf instance of struct nvgpu_nvs_ctrl_queue to contain
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* the constructed buffer metadata.
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* @param bytes size of buffer requested.
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* @param mask Mask of queue requested.
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* @param read_only Indicates whether a read-only buffer is requested.
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* @return int 0 on success, else fail.
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*/
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int nvgpu_nvs_alloc_and_get_buf(struct gk20a *g, struct nvgpu_nvs_ctrl_queue *buf,
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size_t bytes, u8 mask, bool read_only);
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/**
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* @brief Check whether user mappings exist for this buffer.
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*
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* @param g instance of struct gk20a.
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* @param buf instance of struct nvgpu_nvs_ctrl_queue.
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* @return true User mappings exist.
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* @return false User mappings doesn't exist.
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*/
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bool nvgpu_nvs_buf_linux_is_mapped(struct gk20a *g, struct nvgpu_nvs_ctrl_queue *buf);
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#endif /* NVGPU_DMABUF_NVS_H */
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