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git://nv-tegra.nvidia.com/linux-nvgpu.git
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94bc3a8135
Update nvgpu_gr_zbc as:
struct nvgpu_gr_zbc {
struct nvgpu_mutex zbc_lock; /* Lock to access zbc table */
struct zbc_color_table *zbc_col_tbl; /* SW zbc color table pointer */
struct zbc_depth_table *zbc_dep_tbl; /* SW zbc depth table pointer */
struct zbc_stencil_table *zbc_s_tbl; /* SW zbc stencil table pointer */
u32 min_color_index; /* Minimum valid color table index */
u32 min_depth_index; /* Minimum valid depth table index */
u32 min_stencil_index; /* Minimum valid stencil table index */
u32 max_color_index; /* Maximum valid color table index */
u32 max_depth_index; /* Maximum valid depth table index */
u32 max_stencil_index; /* Maximum valid stencil table index */
u32 max_used_color_index; /* Max used color table index */
u32 max_used_depth_index; /* Max used depth table index */
u32 max_used_stencil_index; /* Max used stencil table index */
};
Add global struct nvgpu_gr_zbc_table_indices
struct nvgpu_gr_zbc_table_indices {
u32 min_color_index;
u32 min_depth_index;
u32 min_stencil_index;
u32 max_color_index;
u32 max_depth_index;
u32 max_stencil_index;
};
Currently, hw zbc table registers are written during both
gr_init_setup_sw() and gr_init_setup_hw().
- Modify nvgpu_gr_zbc_load_default_table() to
nvgpu_gr_zbc_load_default_sw_table() to only update sw copy of zbc table
during gr_init_setup_sw().
- Modify nvgpu_gr_zbc_load_table() to write zbc values stored in sw zbc
table to hw registers.
Re-structure zbc function as per zbc type i.e. color, depth and stencil.
Add gr.zbc.init_table_indices() hal to initialize zbc indices. Valid ZBC
table indices start from 1. HW indices start from 0 for color, depth and
stencil tables. Note that the corresponding format registers follow ZBC
index range starting at 1.
- void (*init_table_indices)(struct gk20a *g,
struct nvgpu_gr_zbc_table_indices *zbc_indices);
- Add corresponding functions for legacy chips
- Add zbc color, depth and stencil table size hw defines
- Remove ltc.zbc_table_size() hal
- Update ltc.set_zbc_s_entry(), ltc.set_zbc_color_entry and
ltc.set_zbc_depth_entry() accordingly.
Bug 3122410
Bug 3122649
Change-Id: Ib799991ad35c6613534c0a6eb07f3bf24e600dc5
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2417620
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
90 lines
3.0 KiB
C
90 lines
3.0 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef GR_ZBC_H
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#define GR_ZBC_H
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#include <nvgpu/gr/zbc.h>
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/* Opaque black (i.e. solid black, fmt 0x28 = A8B8G8R8) */
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#define GR_ZBC_SOLID_BLACK_COLOR_FMT 0x28
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/* Transparent black = (fmt 1 = zero) */
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#define GR_ZBC_TRANSPARENT_BLACK_COLOR_FMT 0x1
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/* Opaque white (i.e. solid white) = (fmt 2 = uniform 1) */
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#define GR_ZBC_SOLID_WHITE_COLOR_FMT 0x2
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/* z format with fp32 */
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#define GR_ZBC_Z_FMT_VAL_FP32 0x1
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#define GR_ZBC_STENCIL_CLEAR_FMT_INVAILD 0U
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#define GR_ZBC_STENCIL_CLEAR_FMT_U8 1U
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struct zbc_color_table {
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u32 color_ds[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
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u32 color_l2[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
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u32 format;
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u32 ref_cnt;
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};
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struct zbc_depth_table {
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u32 depth;
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u32 format;
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u32 ref_cnt;
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};
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struct zbc_stencil_table {
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u32 stencil;
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u32 format;
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u32 ref_cnt;
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};
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struct nvgpu_gr_zbc_entry {
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u32 color_ds[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
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u32 color_l2[NVGPU_GR_ZBC_COLOR_VALUE_SIZE];
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u32 depth;
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u32 stencil;
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u32 type;
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u32 format;
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};
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/*
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* HW ZBC table valid entries start at index 1.
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* Entry 0 is reserved to mean "no matching entry found, do not use ZBC"
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*/
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struct nvgpu_gr_zbc {
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struct nvgpu_mutex zbc_lock; /* Lock to access zbc table */
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struct zbc_color_table *zbc_col_tbl; /* SW zbc color table pointer */
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struct zbc_depth_table *zbc_dep_tbl; /* SW zbc depth table pointer */
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struct zbc_stencil_table *zbc_s_tbl; /* SW zbc stencil table pointer */
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u32 min_color_index; /* Minimum valid color table index */
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u32 min_depth_index; /* Minimum valid depth table index */
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u32 min_stencil_index; /* Minimum valid stencil table index */
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u32 max_color_index; /* Maximum valid color table index */
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u32 max_depth_index; /* Maximum valid depth table index */
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u32 max_stencil_index; /* Maximum valid stencil table index */
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u32 max_used_color_index; /* Max used color table index */
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u32 max_used_depth_index; /* Max used depth table index */
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u32 max_used_stencil_index; /* Max used stencil table index */
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};
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#endif /* GR_ZBC_H */
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