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Below HALs are implemented in common.gr unit, but they really belong to common.perf unit since they access registers from perf unit. gops.gr.init_hwpm_pmm_register() gops.gr.get_num_hwpm_perfmon() gops.gr.set_pmm_register() gops.gr.reset_hwpm_pmm_registers() Move them to common.perf unit, and update all the code accordingly gops.perf.init_hwpm_pmm_register() gops.perf.get_num_hwpm_perfmon() gops.perf.set_pmm_register() gops.perf.reset_hwpm_pmm_registers() Add new HAL gops.gr.get_pm_ctx_buffer_offsets() and set it to gr_gk20a_get_pm_ctx_buffer_offsets() for all chips. Bug 2510974 Jira NVGPU-5360 Change-Id: Ib5e84ed5c8b6e72cc6923161e55fc2c3a6a4070e Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2418306 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>