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1f9f28df8c
In gm20b_channel_bind an nvgpu_smp_wmb() was used presumably to prevent MMIO writes from being re-ordered after the memory write to 'ch->bound'. If that was to happen, then unbind routine could observe the channel as bound and issue concurrent MMIO writes to unbind the channel. Assuming, the barrier was to prevent such race, it should have been an nvgpu_wmb(), since nvgpu_smp_wmb() is for inner shareable domain only. However, the race possibility between unbind called from close path and bind from ALLOC_GPFIFO should be ruled out because close will wait for any active devctl/ioctl to finish before proceeding. The race possibility between unbind called from suspend_all_serviceable_ch path and bind from ALLOC_GPFIFO should be ruled out because ALLOC_GPFIFO has power refcount at the start of devctl/ioctl and suspend_all_serviceable_ch is called from prepare_poweroff path which ensure that power refcount is 0. Removed nvgpu_smp_wmb(). Jira NVGPU-4927 Change-Id: Ic4f072df364926c10be84e42b83394c13fc97fdc Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298959 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Shashank Singh <shashsingh@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
69 lines
2.4 KiB
C
69 lines
2.4 KiB
C
/*
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* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/channel.h>
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#include <nvgpu/log.h>
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#include <nvgpu/atomic.h>
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#include <nvgpu/io.h>
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#include <nvgpu/barrier.h>
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#include <nvgpu/mm.h>
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#include <nvgpu/gk20a.h>
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#include "channel_gm20b.h"
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#include <nvgpu/hw/gm20b/hw_ccsr_gm20b.h>
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#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
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void gm20b_channel_bind(struct nvgpu_channel *c)
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{
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struct gk20a *g = c->g;
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u32 inst_ptr = nvgpu_inst_block_ptr(g, &c->inst_block);
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nvgpu_log_info(g, "bind channel %d inst ptr 0x%08x",
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c->chid, inst_ptr);
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nvgpu_writel(g, ccsr_channel_inst_r(c->chid),
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ccsr_channel_inst_ptr_f(inst_ptr) |
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nvgpu_aperture_mask(g, &c->inst_block,
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ccsr_channel_inst_target_sys_mem_ncoh_f(),
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ccsr_channel_inst_target_sys_mem_coh_f(),
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ccsr_channel_inst_target_vid_mem_f()) |
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ccsr_channel_inst_bind_true_f());
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nvgpu_writel(g, ccsr_channel_r(c->chid),
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(nvgpu_readl(g, ccsr_channel_r(c->chid)) &
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~ccsr_channel_enable_set_f(~U32(0U))) |
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ccsr_channel_enable_set_true_f());
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nvgpu_atomic_set(&c->bound, 1);
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}
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void gm20b_channel_force_ctx_reload(struct nvgpu_channel *ch)
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{
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struct gk20a *g = ch->g;
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u32 reg = nvgpu_readl(g, ccsr_channel_r(ch->chid));
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nvgpu_writel(g, ccsr_channel_r(ch->chid),
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reg | ccsr_channel_force_ctx_reload_true_f());
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}
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