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486815f81f
The following violations are fixed in this patch a) misra_c_2012_rule_2_1_violation: This code cannot be reached: "return err;". b) misra_c_2012_directive_4_7_violation: Calling function "nvgpu_preempt_channel(g, ch)" which returns error information without testing the error information. c) misra_c_2012_rule_8_6_violation: "" is declared but never defined for following functions 1) gm20b_dump_engine_status 2) gp10b_ramfc_setup 3) gp10b_ramfc_get_syncpt 4) gp10b_ramfc_set_syncpt 5) gk20a_fifo_intr_0_enable 6) gk20a_fifo_intr_0_isr 7) gk20a_fifo_handle_sched_error 8) gk20a_fifo_is_mmu_fault_pending 9) gk20a_fifo_intr_set_recover_mask 10) gk20a_fifo_intr_unset_recover_mask 11) gk20a_init_fifo_reset_enable_hw 12) gk20a_init_fifo_setup_hw 13) nvgpu_tsg_set_runlist_interleave 14) gm20b_dump_engine_status 15) gp10b_pbdma_channel_fatal_0_intr_descs 16) gp10b_pbdma_allowed_syncpoints_0_index_f 17) gp10b_pbdma_allowed_syncpoints_0_valid_f 18) gp10b_pbdma_allowed_syncpoints_0_index_v 19) gk20a_runlist_reschedule The above functions declarations are now embedded within CONFIG_NVGPU_HAL_NON_FUSA d) The function nvgpu_channel_abort_clean_up has a UMD version and hence its taken out of CONFIG_NVGPU_KERNEL_MODE_SUBMIT to avoid errors of type c above. Jira NVGPU-3881 Change-Id: I5f85c7070e1d2f0b18d14db07ce22a01c29f0e40 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2181032 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
47 lines
1.9 KiB
C
47 lines
1.9 KiB
C
/*
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* Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_FIFO_INTR_GK20A_H
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#define NVGPU_FIFO_INTR_GK20A_H
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#include <nvgpu/types.h>
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struct gk20a;
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#ifdef CONFIG_NVGPU_HAL_NON_FUSA
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void gk20a_fifo_intr_0_enable(struct gk20a *g, bool enable);
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void gk20a_fifo_intr_0_isr(struct gk20a *g);
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bool gk20a_fifo_handle_sched_error(struct gk20a *g);
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bool gk20a_fifo_is_mmu_fault_pending(struct gk20a *g);
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void gk20a_fifo_intr_set_recover_mask(struct gk20a *g);
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void gk20a_fifo_intr_unset_recover_mask(struct gk20a *g);
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#endif
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void gk20a_fifo_intr_1_enable(struct gk20a *g, bool enable);
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u32 gk20a_fifo_intr_1_isr(struct gk20a *g);
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void gk20a_fifo_intr_handle_chsw_error(struct gk20a *g);
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void gk20a_fifo_intr_handle_runlist_event(struct gk20a *g);
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u32 gk20a_fifo_pbdma_isr(struct gk20a *g);
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#endif /* NVGPU_FIFO_INTR_GK20A_H */
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