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3d9c67a0e7
Most of the Orin chip specific code is compiled out of safety build with CONFIG_NVGPU_NON_FUSA and CONFIG_NVGPU_HAL_NON_FUSA. Remove the config protection from Orin/GA10B specific code. Currently all code is enabled. Code not required in safety will be compiled out later in separate activity. Other noteworthy changes in this patch related to safety build: - In ga10b_ce_request_idle(), add a log print to dump num_pce so that compiler does not complain about unused variable num_pce. - In ga10b_fifo_ctxsw_timeout_isr(), protect variables active_eng_id and recover under CONFIG_NVGPU_KERNEL_MODE_SUBMIT to fix compilation errors of unused variables. - Compile out HAL gops.pbdma.force_ce_split() from safety since this HAL is GA100 specific and not required for GA10B. - Compile out gr_ga100_process_context_buffer_priv_segment() with CONFIG_NVGPU_DEBUGGER. - Compile out VAB support with CONFIG_NVGPU_HAL_NON_FUSA. - In ga10b_gr_intr_handle_sw_method(), protect left_shift_by_2 variable with appropriate configs to fix unused variable compilation error. - In ga10b_intr_isr_stall_host2soc_3(), compile ELPG function calls with CONFIG_NVGPU_POWER_PG. - In ga10b_pmu_handle_swgen1_irq(), move whole function body under CONFIG_NVGPU_FALCON_DEBUG to fix unused variable compilation errors. - Add below TU104 specific files in safety build since some of the code in those files is required for GA10B. Unnecessary code will be compiled out later on. hal/gr/init/gr_init_tu104.c hal/class/class_tu104.c hal/mc/mc_tu104.c hal/fifo/usermode_tu104.c hal/gr/falcon/gr_falcon_tu104.c - Compile out GA10B specific debugger/profiler related files from safety build. - Disable CONFIG_NVGPU_FALCON_DEBUG from safety debug build temporarily to work around compilation errors seen with keeping this config enabled. Config will be re-enabled in safety debug build later. Jira NVGPU-7276 Change-Id: I35f2489830ac083d52504ca411c3f1d96e72fc48 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2627048 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
73 lines
2.7 KiB
C
73 lines
2.7 KiB
C
/*
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* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_PBDMA_GA10B_H
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#define NVGPU_PBDMA_GA10B_H
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#include <nvgpu/types.h>
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#define HW_PBDMA_STRIDE 2048U
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#define HW_PBDMA_BASE 0x040000U
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#define PBDMA_PRI_BASE_INVALID U32_MAX
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#define PBDMA_ID_INVALID U32_MAX
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#define INTR_SIZE 0U
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#define INTR_SET_SIZE 1U
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#define INTR_CLEAR_SIZE 2U
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struct gk20a;
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struct nvgpu_debug_context;
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struct nvgpu_pbdma_status_info;
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struct nvgpu_device;
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void ga10b_pbdma_intr_enable(struct gk20a *g, bool enable);
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void ga10b_pbdma_handle_intr(struct gk20a *g, u32 pbdma_id, bool recover);
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bool ga10b_pbdma_handle_intr_0(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0,
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u32 *error_notifier);
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bool ga10b_pbdma_handle_intr_1(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_1,
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u32 *error_notifier);
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u32 ga10b_pbdma_read_data(struct gk20a *g, u32 pbdma_id);
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void ga10b_pbdma_reset_header(struct gk20a *g, u32 pbdma_id);
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void ga10b_pbdma_reset_method(struct gk20a *g, u32 pbdma_id,
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u32 pbdma_method_index);
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void ga10b_pbdma_clear_all_intr(struct gk20a *g, u32 pbdma_id);
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void ga10b_pbdma_disable_and_clear_all_intr(struct gk20a *g);
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u32 ga10b_pbdma_channel_fatal_0_intr_descs(void);
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u32 ga10b_pbdma_device_fatal_0_intr_descs(void);
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u32 ga10b_pbdma_set_channel_info_chid(u32 chid);
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u32 ga10b_pbdma_set_intr_notify(u32 eng_intr_vector);
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u32 ga10b_pbdma_set_clear_intr_offsets(struct gk20a *g,
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u32 set_clear_size);
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u32 ga10b_pbdma_get_fc_target(const struct nvgpu_device *dev);
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void ga10b_pbdma_dump_status(struct gk20a *g, struct nvgpu_debug_context *o);
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u32 ga10b_pbdma_get_mmu_fault_id(struct gk20a *g, u32 pbdma_id);
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u32 ga10b_pbdma_get_num_of_pbdmas(void);
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#endif /* NVGPU_PBDMA_GA10B_H */
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