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git://nv-tegra.nvidia.com/linux-nvgpu.git
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e0dd79cd43
Remove current mc hals - mc.reset() - mc.enable() - mc.disable() - mc.reset_mask() - mc.reset_engine() - mc.reset_engine_enable() Add new mc hals - mc.enable_units(g, units, enable) > enable/disable given unit(s) - mc.enable_dev(g, dev, enable) > enable/disable engine represented by given device pointer - mc.enable_devtype(g, devtype) > enable/disable all engines of given devtype Move common mc intr functions to common/mc/mc_intr.c. Add below common mc functions - nvgpu_mc_reset_units(g, units) > reset given logical OR of nvgpu unit bitmap - nvgpu_mc_reset_dev(g, dev) > reset given single engine via dev > if engine is graphics, reset gpcs for nvgpu_next - nvgpu_mc_reset_devtype(g, devtype) > reset all engines of given devtype > if devtype is graphics, reset gpcs for nvgpu_next Bug 200648985 Bug 3109773 Change-Id: Idc67a14a0a7cde83de44fbfbec13007fead3ed5c Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2408523 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
60 lines
2.4 KiB
C
60 lines
2.4 KiB
C
/*
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* Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef NVGPU_MC_GP10B_H
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#define NVGPU_MC_GP10B_H
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#include <nvgpu/types.h>
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#ifdef CONFIG_NVGPU_NON_FUSA
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#define MAX_MC_INTR_REGS 2U
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#endif
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struct gk20a;
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struct nvgpu_device;
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enum nvgpu_fifo_engine;
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void mc_gp10b_intr_mask(struct gk20a *g);
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void mc_gp10b_intr_stall_unit_config(struct gk20a *g, u32 unit, bool enable);
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void mc_gp10b_intr_nonstall_unit_config(struct gk20a *g, u32 unit, bool enable);
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void mc_gp10b_isr_stall_secondary_1(struct gk20a *g, u32 mc_intr_0);
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void mc_gp10b_isr_stall_secondary_0(struct gk20a *g, u32 mc_intr_0);
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void mc_gp10b_isr_stall_engine(struct gk20a *g, const struct nvgpu_device *dev);
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void mc_gp10b_isr_stall(struct gk20a *g);
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bool mc_gp10b_is_intr1_pending(struct gk20a *g, u32 unit, u32 mc_intr_1);
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#ifdef CONFIG_NVGPU_NON_FUSA
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void mc_gp10b_log_pending_intrs(struct gk20a *g);
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#endif
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u32 mc_gp10b_intr_stall(struct gk20a *g);
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void mc_gp10b_intr_stall_pause(struct gk20a *g);
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void mc_gp10b_intr_stall_resume(struct gk20a *g);
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u32 mc_gp10b_intr_nonstall(struct gk20a *g);
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void mc_gp10b_intr_nonstall_pause(struct gk20a *g);
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void mc_gp10b_intr_nonstall_resume(struct gk20a *g);
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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void mc_gp10b_ltc_isr(struct gk20a *g);
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/** @endcond DOXYGEN_SHOULD_SKIP_THIS */
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#endif /* NVGPU_MC_GP10B_H */
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